TimeQuest Timing Analyzer report for atari800core
Sun May 31 21:28:16 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'FPGA_CLK'
 27. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'FPGA_CLK'
 31. Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Output Enable Times
 47. Minimum Output Enable Times
 48. Output Disable Times
 49. Minimum Output Disable Times
 50. Slow 1200mV 85C Model Metastability Report
 51. Slow 1200mV 0C Model Fmax Summary
 52. Slow 1200mV 0C Model Setup Summary
 53. Slow 1200mV 0C Model Hold Summary
 54. Slow 1200mV 0C Model Recovery Summary
 55. Slow 1200mV 0C Model Removal Summary
 56. Slow 1200mV 0C Model Minimum Pulse Width Summary
 57. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 58. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 59. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 61. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 65. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 69. Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Recovery: 'FPGA_CLK'
 71. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 74. Slow 1200mV 0C Model Removal: 'FPGA_CLK'
 75. Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 78. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 80. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 81. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 86. Setup Times
 87. Hold Times
 88. Clock to Output Times
 89. Minimum Clock to Output Times
 90. Output Enable Times
 91. Minimum Output Enable Times
 92. Output Disable Times
 93. Minimum Output Disable Times
 94. Slow 1200mV 0C Model Metastability Report
 95. Fast 1200mV 0C Model Setup Summary
 96. Fast 1200mV 0C Model Hold Summary
 97. Fast 1200mV 0C Model Recovery Summary
 98. Fast 1200mV 0C Model Removal Summary
 99. Fast 1200mV 0C Model Minimum Pulse Width Summary
100. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
103. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
104. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
106. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
108. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
111. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
112. Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
113. Fast 1200mV 0C Model Recovery: 'FPGA_CLK'
114. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
116. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
117. Fast 1200mV 0C Model Removal: 'FPGA_CLK'
118. Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
119. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
120. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
121. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
122. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
123. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
124. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
125. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
126. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
127. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
129. Setup Times
130. Hold Times
131. Clock to Output Times
132. Minimum Clock to Output Times
133. Output Enable Times
134. Minimum Output Enable Times
135. Output Disable Times
136. Minimum Output Disable Times
137. Fast 1200mV 0C Model Metastability Report
138. Multicorner Timing Analysis Summary
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Board Trace Model Assignments
144. Input Transition Times
145. Slow Corner Signal Integrity Metrics
146. Fast Corner Signal Integrity Metrics
147. Setup Transfers
148. Hold Transfers
149. Recovery Transfers
150. Removal Transfers
151. Report TCCS
152. Report RSKM
153. Unconstrained Paths
154. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.62        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-6         ;  12.5%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sun May 31 21:28:08 2020 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Clock Name                                                                          ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                             ; Source                                                                                ; Targets                                                                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                            ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                    ;                                                                                       ; { FPGA_CLK }                                                                            ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                 ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 33.78 MHz  ; 33.78 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 73.59 MHz  ; 73.59 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 79.72 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
; 108.68 MHz ; 108.68 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 128.21 MHz ; 128.21 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                          ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.085 ; -156.488      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.027 ; -2.027        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.348 ; -6.231        ;
; FPGA_CLK                                                                            ; -0.118 ; -0.118        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.601  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.958  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.935 ; -71.462       ;
; FPGA_CLK                                                                            ; -0.788 ; -0.788        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.406  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.455  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.872 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                       ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.760 ; -24.728       ;
; FPGA_CLK                                                                            ; -0.615 ; -15.989       ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.634  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.639  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.557 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.271 ; -6.996        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.454  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.538  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.539  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.287  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.568  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.696  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.506  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.346  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.188 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.588 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.418 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -4.085 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.413      ;
; -3.984 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.312      ;
; -3.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.646     ; 1.267      ;
; -3.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.133      ;
; -3.793 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.646     ; 1.119      ;
; -3.775 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.103      ;
; -3.771 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.646     ; 1.097      ;
; -3.762 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.646     ; 1.088      ;
; -3.625 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 1.383      ;
; -3.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.645     ; 0.907      ;
; -3.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.645     ; 0.907      ;
; -3.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 1.316      ;
; -3.556 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.645     ; 0.883      ;
; -3.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 1.277      ;
; -3.374 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 1.132      ;
; -3.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 1.094      ;
; -3.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 1.094      ;
; -3.296 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.175     ; 1.093      ;
; -3.193 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 0.934      ;
; -3.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 0.907      ;
; -3.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 0.907      ;
; -3.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 0.907      ;
; -3.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.231     ; 0.907      ;
; -3.152 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.216     ; 0.908      ;
; -3.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 0.909      ;
; -3.150 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 0.908      ;
; -3.150 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.216     ; 0.906      ;
; -3.149 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.908      ;
; -3.149 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.908      ;
; -3.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.906      ;
; -3.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.214     ; 0.895      ;
; -3.130 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.220     ; 0.882      ;
; -3.129 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.220     ; 0.881      ;
; -3.129 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.220     ; 0.881      ;
; -3.124 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.883      ;
; -3.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.881      ;
; -3.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.213     ; 0.881      ;
; -3.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.175     ; 0.909      ;
; -3.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.175     ; 0.909      ;
; -3.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.175     ; 0.907      ;
; -3.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.175     ; 0.906      ;
; -3.100 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.189     ; 0.883      ;
; -3.098 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.189     ; 0.881      ;
; -3.096 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.186     ; 0.882      ;
; -3.094 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.186     ; 0.880      ;
; -3.075 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.163     ; 0.884      ;
; -3.074 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.163     ; 0.883      ;
; 1.939  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 9.520      ;
; 1.943  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 9.516      ;
; 1.943  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 9.516      ;
; 1.971  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.193     ; 9.495      ;
; 2.039  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.421      ;
; 2.074  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 9.397      ;
; 2.173  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 9.291      ;
; 2.178  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.282      ;
; 2.178  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.282      ;
; 2.229  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 9.241      ;
; 2.229  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 9.241      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.292  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.168      ;
; 2.310  ; ram_do_reg[1]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 9.166      ;
; 2.334  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 9.131      ;
; 2.337  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 9.131      ;
; 2.342  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 9.127      ;
; 2.343  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.196     ; 9.120      ;
; 2.401  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 9.058      ;
; 2.404  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.196     ; 9.059      ;
; 2.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.030      ;
; 2.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 9.030      ;
; 2.473  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 8.994      ;
; 2.478  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 8.982      ;
; 2.478  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 8.982      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.495  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.963      ;
; 2.510  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.193     ; 8.956      ;
; 2.545  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.914      ;
; 2.552  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.903      ;
; 2.552  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.903      ;
; 2.584  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 8.881      ;
; 2.589  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.866      ;
; 2.589  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.866      ;
; 2.589  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 8.866      ;
; 2.593  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 8.874      ;
; 2.610  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 8.855      ;
; 2.612  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 8.852      ;
; 2.627  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[5]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.830      ;
; 2.627  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 8.830      ;
; 2.627  ; ram_do_reg[1]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 8.849      ;
; 2.634  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.825      ;
; 2.634  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.825      ;
; 2.634  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.825      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -2.027 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.955     ; 1.307      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.348 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.566      ;
; -0.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.575      ;
; -0.331 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.561      ;
; -0.328 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.558      ;
; -0.322 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.540      ;
; -0.312 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.530      ;
; -0.294 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.524      ;
; -0.293 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.523      ;
; -0.281 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.342      ; 1.523      ;
; -0.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.465      ;
; -0.240 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.458      ;
; -0.232 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.450      ;
; -0.230 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.448      ;
; -0.225 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.455      ;
; -0.224 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.442      ;
; -0.217 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.435      ;
; -0.213 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.443      ;
; -0.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.422      ;
; -0.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.422      ;
; -0.123 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.340      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.333      ;
; -0.097 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.314      ;
; -0.094 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.312      ;
; -0.083 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.301      ;
; -0.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.297      ;
; -0.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.292      ;
; -0.072 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.290      ;
; -0.057 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.275      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.279      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.342      ; 1.290      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.266      ;
; -0.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.342      ; 1.289      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.343      ; 1.283      ;
; -0.033 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.342      ; 1.275      ;
; -0.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.343      ; 1.268      ;
; -0.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.240      ;
; -0.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.318      ; 1.239      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.343      ; 1.252      ;
; -0.002 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.232      ;
; 0.001  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 1.229      ;
; 0.099  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 1.118      ;
; 3.622  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.827     ; 8.359      ;
; 3.919  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.828     ; 8.061      ;
; 5.354  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.436     ; 7.018      ;
; 6.869  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 5.517      ;
; 7.018  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 5.368      ;
; 7.092  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 5.294      ;
; 7.210  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.017      ; 7.225      ;
; 7.240  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 5.146      ;
; 7.342  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.018      ; 7.094      ;
; 7.398  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.017      ; 7.037      ;
; 7.431  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.955      ;
; 7.462  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 4.923      ;
; 7.463  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 4.922      ;
; 7.501  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.018      ; 6.935      ;
; 7.548  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.018      ; 6.888      ;
; 7.617  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.769      ;
; 7.654  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.732      ;
; 7.662  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 4.741      ;
; 7.672  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 4.731      ;
; 7.689  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 4.696      ;
; 7.720  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.018      ; 6.716      ;
; 7.765  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.621      ;
; 7.818  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 4.567      ;
; 7.819  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.017      ; 6.616      ;
; 7.839  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.547      ;
; 7.874  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 4.529      ;
; 7.987  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.399      ;
; 7.995  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 4.408      ;
; 8.277  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 4.108      ;
; 8.347  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 4.056      ;
; 8.555  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 3.848      ;
; 8.767  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 3.618      ;
; 8.824  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.423     ; 3.561      ;
; 8.909  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.405     ; 3.494      ;
; 9.214  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.110     ; 1.093      ;
; 9.216  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.110     ; 1.091      ;
; 11.432 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 9.310      ;
; 11.576 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.108     ; 9.150      ;
; 11.605 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 9.137      ;
; 11.775 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.108     ; 8.951      ;
; 11.790 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.108     ; 8.936      ;
; 11.965 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.108     ; 8.761      ;
; 12.051 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 8.691      ;
; 12.132 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 8.622      ;
; 12.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[3]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 8.615      ;
; 12.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.355      ;
; 12.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.355      ;
; 12.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.355      ;
; 12.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.325      ;
; 12.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.325      ;
; 12.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.091     ; 8.325      ;
; 12.505 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 8.249      ;
; 12.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.185      ;
; 12.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.185      ;
; 12.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.185      ;
; 12.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.950      ;
; 12.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.950      ;
; 12.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.950      ;
; 12.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.843      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.118  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.624      ; 4.509      ;
; 93.728  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.728     ; 5.545      ;
; 95.957  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.523      ; 1.765      ;
; 196.363 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.560      ;
; 196.393 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.530      ;
; 196.485 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.438      ;
; 196.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.415      ;
; 196.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.414      ;
; 196.538 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.385      ;
; 196.539 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.384      ;
; 196.598 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.325      ;
; 196.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.296      ;
; 196.631 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.292      ;
; 196.654 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.269      ;
; 196.655 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.268      ;
; 196.655 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.268      ;
; 196.684 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.239      ;
; 196.685 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.238      ;
; 196.685 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.238      ;
; 196.744 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.179      ;
; 196.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.172      ;
; 196.756 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.167      ;
; 196.773 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.150      ;
; 196.777 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.146      ;
; 196.798 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.125      ;
; 196.800 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.123      ;
; 196.801 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.122      ;
; 196.801 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.122      ;
; 196.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.095      ;
; 196.830 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.093      ;
; 196.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.092      ;
; 196.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.092      ;
; 196.885 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.038      ;
; 196.890 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.033      ;
; 196.897 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.026      ;
; 196.902 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.021      ;
; 196.919 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.004      ;
; 196.923 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 3.000      ;
; 196.924 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.999      ;
; 196.944 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.979      ;
; 196.946 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.977      ;
; 196.947 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.976      ;
; 196.947 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.976      ;
; 196.948 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.975      ;
; 196.974 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.949      ;
; 196.976 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.947      ;
; 196.977 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.946      ;
; 196.977 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.946      ;
; 196.978 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.945      ;
; 197.031 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.892      ;
; 197.036 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.887      ;
; 197.037 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.886      ;
; 197.043 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.880      ;
; 197.048 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.875      ;
; 197.065 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.858      ;
; 197.069 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.854      ;
; 197.070 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.853      ;
; 197.070 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.853      ;
; 197.090 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.833      ;
; 197.091 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.832      ;
; 197.092 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.831      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.830      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.830      ;
; 197.094 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.829      ;
; 197.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.803      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.802      ;
; 197.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.801      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.800      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.800      ;
; 197.124 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.799      ;
; 197.177 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.746      ;
; 197.182 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.741      ;
; 197.183 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.740      ;
; 197.183 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.740      ;
; 197.189 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.734      ;
; 197.194 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.729      ;
; 197.211 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.712      ;
; 197.215 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.708      ;
; 197.216 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.707      ;
; 197.216 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.707      ;
; 197.216 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.707      ;
; 197.236 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.687      ;
; 197.237 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.686      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.684      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.684      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.685      ;
; 197.239 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.684      ;
; 197.240 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.683      ;
; 197.266 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.657      ;
; 197.267 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.656      ;
; 197.268 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.654      ;
; 197.268 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.655      ;
; 197.269 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.654      ;
; 197.269 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.654      ;
; 197.270 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.653      ;
; 197.323 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.600      ;
; 197.327 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.596      ;
; 197.328 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.595      ;
; 197.329 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.594      ;
; 197.329 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.078     ; 2.594      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.601 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 4.873      ;
; 0.601 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 4.873      ;
; 0.660 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.816      ;
; 0.746 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 4.728      ;
; 0.746 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 4.728      ;
; 0.794 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.682      ;
; 0.904 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.571      ;
; 0.914 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.562      ;
; 1.049 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.426      ;
; 1.059 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 4.417      ;
; 1.103 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.374      ;
; 1.248 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.229      ;
; 1.258 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.183     ; 4.213      ;
; 1.383 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.105      ;
; 1.393 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 4.071      ;
; 1.441 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 4.048      ;
; 1.477 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.186     ; 3.991      ;
; 1.489 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 4.000      ;
; 1.517 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.971      ;
; 1.573 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.188     ; 3.893      ;
; 1.586 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.903      ;
; 1.621 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.843      ;
; 1.634 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.855      ;
; 1.644 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.839      ;
; 1.670 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.828      ;
; 1.693 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.771      ;
; 1.795 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.832      ;
; 1.807 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.820      ;
; 1.866 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.188     ; 3.600      ;
; 1.878 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.749      ;
; 1.879 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.748      ;
; 1.920 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.544      ;
; 1.921 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.706      ;
; 1.922 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.705      ;
; 1.922 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.705      ;
; 1.926 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.188     ; 3.540      ;
; 1.937 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.188     ; 3.529      ;
; 1.966 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.661      ;
; 1.967 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.660      ;
; 1.967 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.660      ;
; 1.967 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.660      ;
; 1.967 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.660      ;
; 1.968 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.659      ;
; 1.968 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.659      ;
; 2.076 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.412      ;
; 2.080 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.538      ;
; 2.097 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.530      ;
; 2.101 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.526      ;
; 2.145 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.327      ;
; 2.148 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.486      ;
; 2.148 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.486      ;
; 2.156 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.462      ;
; 2.190 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.433      ;
; 2.209 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.425      ;
; 2.209 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.425      ;
; 2.215 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.408      ;
; 2.215 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.407      ;
; 2.216 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.406      ;
; 2.218 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.405      ;
; 2.218 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.405      ;
; 2.219 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.403      ;
; 2.220 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.402      ;
; 2.221 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.267      ;
; 2.242 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.380      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.378      ;
; 2.258 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.364      ;
; 2.259 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.374      ;
; 2.259 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.374      ;
; 2.259 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.363      ;
; 2.259 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.363      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.288 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.333      ;
; 2.289 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.347      ;
; 2.334 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.298      ;
; 2.334 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.298      ;
; 2.334 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.298      ;
; 2.334 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.298      ;
; 2.378 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.955     ; 1.308      ;
; 2.379 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.114      ;
; 2.382 ; SDRAM_ADDR[0]                                                                             ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.236      ;
; 2.398 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.224      ;
; 2.416 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.071      ;
; 2.427 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.195      ;
; 2.446 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.176      ;
; 2.449 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.173      ;
; 2.466 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.022      ;
; 2.466 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.022      ;
; 2.466 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.022      ;
; 2.466 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.022      ;
; 2.466 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 3.015      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 4.958  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.955     ; 1.665      ;
; 8.420  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 8.832      ;
; 8.495  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 8.757      ;
; 8.786  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.263     ; 8.353      ;
; 8.786  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 8.518      ;
; 9.187  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 8.065      ;
; 9.200  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 8.104      ;
; 9.326  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 7.865      ;
; 9.539  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.765      ;
; 9.566  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 7.686      ;
; 9.644  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.660      ;
; 9.656  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.647      ;
; 9.669  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.246     ; 7.487      ;
; 9.726  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.577      ;
; 9.752  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 7.439      ;
; 9.783  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.486      ;
; 9.798  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.506      ;
; 9.798  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.471      ;
; 9.803  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 7.449      ;
; 9.804  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.500      ;
; 9.834  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.470      ;
; 9.834  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.469      ;
; 9.852  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.451      ;
; 9.858  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 7.394      ;
; 9.859  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.445      ;
; 9.878  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 7.392      ;
; 9.891  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 7.361      ;
; 9.910  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.245     ; 7.247      ;
; 9.953  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.351      ;
; 10.011 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 7.180      ;
; 10.018 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.251      ;
; 10.019 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 7.251      ;
; 10.062 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 7.128      ;
; 10.069 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 7.201      ;
; 10.078 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.191      ;
; 10.108 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.195      ;
; 10.113 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.191      ;
; 10.118 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.186      ;
; 10.119 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.185      ;
; 10.121 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.182      ;
; 10.144 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.125      ;
; 10.149 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.155      ;
; 10.164 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.133     ; 7.105      ;
; 10.167 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 7.023      ;
; 10.201 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.103      ;
; 10.209 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.095      ;
; 10.215 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.089      ;
; 10.243 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 7.061      ;
; 10.248 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 6.832      ;
; 10.248 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.055      ;
; 10.278 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.462     ; 6.792      ;
; 10.287 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.016      ;
; 10.301 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.462     ; 6.769      ;
; 10.309 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.995      ;
; 10.310 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 6.770      ;
; 10.316 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.987      ;
; 10.324 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.979      ;
; 10.331 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 6.860      ;
; 10.342 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 6.910      ;
; 10.355 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 6.836      ;
; 10.386 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.918      ;
; 10.387 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.916      ;
; 10.393 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 6.877      ;
; 10.409 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.895      ;
; 10.411 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.892      ;
; 10.418 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.886      ;
; 10.422 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.263     ; 6.717      ;
; 10.456 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 6.735      ;
; 10.462 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.842      ;
; 10.482 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 6.788      ;
; 10.527 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.777      ;
; 10.562 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 6.518      ;
; 10.563 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.741      ;
; 10.589 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 6.477      ;
; 10.612 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 6.454      ;
; 10.673 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.631      ;
; 10.684 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.465     ; 6.383      ;
; 10.692 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.612      ;
; 10.779 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.525      ;
; 10.793 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 6.477      ;
; 10.816 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.488      ;
; 10.884 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.420      ;
; 10.893 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 6.359      ;
; 10.935 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.223     ; 6.244      ;
; 10.984 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.465     ; 6.083      ;
; 10.998 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.465     ; 6.069      ;
; 11.004 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.300      ;
; 11.014 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.290      ;
; 11.026 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.278      ;
; 11.068 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.236      ;
; 11.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg                                                           ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.210     ; 6.096      ;
; 11.134 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 6.118      ;
; 11.165 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 6.087      ;
; 11.206 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 6.046      ;
; 11.252 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.052      ;
; 11.328 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 5.924      ;
; 11.466 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 5.786      ;
; 11.587 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.465     ; 5.480      ;
; 11.689 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.462     ; 5.381      ;
; 11.720 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.360      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                               ; To Node                                                                                                                                                                                                 ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.935 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.018      ;
; -1.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.044      ;
; -1.923 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.042      ;
; -1.919 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.058      ;
; -1.917 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.060      ;
; -1.917 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.036      ;
; -1.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.062      ;
; -1.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.079      ;
; -1.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.056      ;
; -1.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.059      ;
; -1.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.061      ;
; -1.886 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.067      ;
; -1.870 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.083      ;
; -1.861 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.091      ;
; -1.845 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.107      ;
; -1.832 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.133      ;
; -1.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.151      ;
; -1.810 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.142      ;
; -1.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.147      ;
; -1.784 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.193      ;
; -1.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.230      ;
; -1.719 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.246      ;
; -1.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.240      ;
; -1.710 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.243      ;
; -1.706 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.247      ;
; -1.702 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.251      ;
; -1.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.252      ;
; -1.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.264      ;
; -1.697 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.256      ;
; -1.678 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.631      ; 1.273      ;
; -1.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.290      ;
; -1.632 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.321      ;
; -1.541 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.657      ; 1.436      ;
; -1.531 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.434      ;
; -1.527 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.438      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.457      ;
; -1.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.448      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.463      ;
; -1.490 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.632      ; 1.462      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 1.477      ;
; -1.481 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.633      ; 1.472      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                  ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.788 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.527      ; 4.117      ;
; 0.502  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.793      ;
; 0.505  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.796      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.801      ;
; 0.746  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.037      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.751  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.752  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.043      ;
; 0.752  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.043      ;
; 0.766  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.057      ;
; 0.766  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.057      ;
; 0.773  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.064      ;
; 1.100  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.391      ;
; 1.101  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.101  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.103  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.394      ;
; 1.103  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.394      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.110  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.113  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.404      ;
; 1.113  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.404      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.411      ;
; 1.121  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.122  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.413      ;
; 1.122  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.413      ;
; 1.127  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.418      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.427      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.190  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.482      ;
; 1.231  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.523      ;
; 1.231  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.522      ;
; 1.232  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.234  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.525      ;
; 1.234  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.525      ;
; 1.240  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.532      ;
; 1.240  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.531      ;
; 1.241  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.243  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.534      ;
; 1.248  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.540      ;
; 1.248  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.540      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                ; To Node                                                                                                                                                                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.140      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[3]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.480      ; 1.145      ;
; 0.435 ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                               ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                               ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                    ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; paddle_mode_reg                                                                                                                          ; paddle_mode_reg                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.505 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.796      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.538 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.830      ;
; 0.643 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.934      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.936      ;
; 0.676 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.968      ;
; 0.703 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.703 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.742 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.745 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.036      ;
; 0.748 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.042      ;
; 0.757 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.758 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.760 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.052      ;
; 0.777 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.068      ;
; 0.783 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.074      ;
; 0.852 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.143      ;
; 0.942 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.234      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.268      ;
; 0.976 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.267      ;
; 1.005 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.296      ;
; 1.064 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.356      ;
; 1.064 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.361      ;
; 1.065 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.356      ;
; 1.084 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.381      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.384      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.386      ;
; 1.095 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.385      ;
; 1.097 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.387      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.396      ;
; 1.105 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.398      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.135 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.422      ;
; 1.135 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.422      ;
; 1.171 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.462      ;
; 1.182 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.472      ;
; 1.193 ; seq_reg[1]                                                ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.484      ;
; 1.195 ; seq_reg[1]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.486      ;
; 1.203 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.494      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.514      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.514      ;
; 1.223 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.515      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.523      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.523      ;
; 1.232 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.534      ;
; 1.243 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.534      ;
; 1.249 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.541      ;
; 1.249 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.541      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.542      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.543      ;
; 1.256 ; seq_reg[0]                                                ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.547      ;
; 1.258 ; seq_reg[0]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.549      ;
; 1.283 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.580      ;
; 1.288 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.574      ;
; 1.289 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.575      ;
; 1.297 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.586      ;
; 1.298 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.587      ;
; 1.309 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.600      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                     ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; half_scandouble_enable_reg                                                    ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.758      ;
; 0.502 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.793      ;
; 0.502 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.793      ;
; 0.502 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.510 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.801      ;
; 0.686 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.977      ;
; 0.687 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.978      ;
; 0.689 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.979      ;
; 0.689 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.979      ;
; 0.689 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.979      ;
; 0.692 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.985      ;
; 0.697 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.989      ;
; 0.697 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.988      ;
; 0.697 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.988      ;
; 0.697 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.987      ;
; 0.699 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.990      ;
; 0.699 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.872 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.673     ; 1.099      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.760 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.319      ; 3.979      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.746 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.324      ; 3.970      ;
; -2.539 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.317      ; 3.821      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
; -2.525 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.322      ; 3.812      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.609      ; 4.991      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.615 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.610      ; 4.992      ;
; -0.614 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.615      ; 4.996      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.634 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.825      ;
; 7.634 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 3.830      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.635 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.205     ; 3.819      ;
; 7.639 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 3.819      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 3.821      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.817      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[8]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.193     ; 3.823      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[10]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.824      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 3.821      ;
; 7.643 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 3.821      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.815      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.815      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.815      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack1         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.824      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.815      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 3.815      ;
; 7.644 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.194     ; 3.821      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 3.827      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.832      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.645 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.829      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.198     ; 3.815      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.184     ; 3.829      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[17]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.184     ; 3.829      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.184     ; 3.829      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.646 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.827      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.822      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.827      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.822      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.196     ; 3.816      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.827      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.827      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.821      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.813      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.195     ; 3.817      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.813      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[6]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.813      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.821      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[7]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.813      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 3.820      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[4]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.199     ; 3.813      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.391     ; 3.486      ;
; 7.640 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.393     ; 3.483      ;
; 7.641 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.491      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.395     ; 3.479      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.395     ; 3.479      ;
; 7.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.395     ; 3.479      ;
; 7.643 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.409     ; 3.464      ;
; 7.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.476      ;
; 7.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.408     ; 3.463      ;
; 7.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.408     ; 3.463      ;
; 7.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.408     ; 3.463      ;
; 7.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.413     ; 3.458      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.409     ; 3.461      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.409     ; 3.461      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.409     ; 3.461      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 3.657      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 3.655      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.654      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.228     ; 3.654      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 3.656      ;
; 7.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 3.656      ;
; 7.647 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.472      ;
; 7.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.264     ; 3.613      ;
; 7.652 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.266     ; 3.610      ;
; 7.653 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.618      ;
; 7.654 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.268     ; 3.606      ;
; 7.654 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.268     ; 3.606      ;
; 7.654 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.268     ; 3.606      ;
; 7.655 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.282     ; 3.591      ;
; 7.656 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.603      ;
; 7.657 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.286     ; 3.585      ;
; 7.657 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.281     ; 3.590      ;
; 7.657 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.281     ; 3.590      ;
; 7.657 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.281     ; 3.590      ;
; 7.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.282     ; 3.588      ;
; 7.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.282     ; 3.588      ;
; 7.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.282     ; 3.588      ;
; 7.659 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.599      ;
; 7.665 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.650      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.666 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.648      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.692      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.699      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.699      ;
; 7.799 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.650      ;
; 7.799 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.650      ;
; 7.802 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.658      ;
; 7.802 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.658      ;
; 7.802 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.658      ;
; 7.802 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 3.658      ;
; 7.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 7.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 7.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 3.367      ;
; 7.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 3.367      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.222      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.222      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.222      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.226      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.226      ;
; 8.236 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.222      ;
; 8.237 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.232      ;
; 8.239 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.205      ;
; 8.239 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.205      ;
; 8.239 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.206      ;
; 8.240 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 3.209      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.209      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.209      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.209      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.209      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.214      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.214      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.214      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.214      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.212      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
; 8.241 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.206      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                           ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.557 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.624      ;
; 11.557 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.624      ;
; 11.557 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.624      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.623      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.222     ; 5.622      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.623      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.222     ; 5.622      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.222     ; 5.622      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.623      ;
; 11.558 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.221     ; 5.623      ;
; 11.564 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.273     ; 5.565      ;
; 11.564 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.273     ; 5.565      ;
; 11.596 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.255     ; 5.551      ;
; 11.596 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.256     ; 5.550      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 11.626 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.704      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 5.213      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.103 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 5.212      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.104 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 5.210      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
; 12.115 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 5.215      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.271 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.519      ; 4.626      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.513      ; 4.622      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
; -0.269 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.514      ; 4.623      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.636      ; 3.527      ;
; 0.471 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.631      ; 3.539      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.734 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.640      ; 3.694      ;
; 0.751 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.635      ; 3.706      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                 ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.538 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.678      ; 3.539      ;
; 2.538 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.678      ; 3.539      ;
; 2.538 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.678      ; 3.539      ;
; 2.538 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.678      ; 3.539      ;
; 2.542 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.671      ; 3.536      ;
; 2.542 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.671      ; 3.536      ;
; 2.542 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.671      ; 3.536      ;
; 2.812 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.682      ; 3.706      ;
; 2.812 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.682      ; 3.706      ;
; 2.812 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.682      ; 3.706      ;
; 2.812 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.682      ; 3.706      ;
; 2.816 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.675      ; 3.703      ;
; 2.816 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.675      ; 3.703      ;
; 2.816 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.675      ; 3.703      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.196      ; 3.529      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.189      ; 3.522      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.189      ; 3.522      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 3.531      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[24]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[30]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[30]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.189      ; 3.522      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.189      ; 3.522      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[31]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[31]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.189      ; 3.522      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[23]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[20]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[22]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[22]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 3.531      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[21]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[21]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 3.531      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 3.531      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[19]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.525      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.195      ; 3.528      ;
; 3.010 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.186      ; 3.520      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.184      ; 3.518      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.184      ; 3.518      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.186      ; 3.520      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.527      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.527      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.184      ; 3.518      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.193      ; 3.527      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
; 3.011 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.192      ; 3.526      ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.539 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.035      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.539 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.037      ;
; 2.540 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.038      ;
; 2.540 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.038      ;
; 2.540 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.038      ;
; 2.540 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.038      ;
; 2.540 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 3.041      ;
; 2.541 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 3.053      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.033      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.033      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 3.043      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 3.043      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 3.043      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.046      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.033      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 3.046      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 3.043      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.033      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.035      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 3.031      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.037      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.037      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.037      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.037      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.038      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.037      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.542 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.034      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 3.029      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 3.029      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.030      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.543 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.033      ;
; 2.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.188      ;
; 2.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.188      ;
; 2.782 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.188      ;
; 2.782 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.188      ;
; 2.949 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.440      ;
; 2.949 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 3.440      ;
; 2.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.453      ;
; 2.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 3.454      ;
; 2.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.453      ;
; 2.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 3.454      ;
; 2.998 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.490      ;
; 3.001 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.181      ; 3.503      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                           ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.287 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.786      ;
; 4.287 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.179      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 4.787      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.288 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 4.788      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.300 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.786      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 4.786      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
; 4.301 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 4.787      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.568 ; 5.788        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.569 ; 5.789        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.665 ; 5.823        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.666 ; 5.824        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[4]                   ;
; 5.666 ; 5.824        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[7]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.696 ; 5.840        ; 0.144          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.781 ; 5.905        ; 0.124          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.840 ; 5.840        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.905 ; 5.905        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                            ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ;
; 8.506 ; 8.726        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                          ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ;
; 8.509 ; 8.729        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                    ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ;
; 8.510 ; 8.730        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.346  ; 10.376       ; 1.030          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                     ;
; 9.425  ; 10.455       ; 1.030          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                     ;
; 10.108 ; 10.328       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                  ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                             ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn       ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn               ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]                   ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                              ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                                 ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                            ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                         ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]                           ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]                           ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]                           ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                      ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                 ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                 ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]             ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]             ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]             ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.188 ; 17.589       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.230 ; 17.631       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.288 ; 17.508       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]           ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]           ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq           ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1]         ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]          ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]          ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq               ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]       ;
; 17.307 ; 17.527       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]          ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg                                                                                                                                              ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                             ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[0]                                                                                                            ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[1]                                                                                                            ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                       ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                               ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[1]                                                                                                          ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.588 ; 17.588       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.588 ; 17.588       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.588 ; 17.588       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.588 ; 17.588       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.588 ; 17.588       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.590 ; 17.590       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.649 ; 17.649       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.651 ; 17.651       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.651 ; 17.651       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                            ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.418 ; 99.720       ; 10.302         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.972 ; 100.274      ; 10.302         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.720 ; 99.720       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.752 ; 99.752       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.758 ; 99.946       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.760 ; 99.948       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.765 ; 99.765       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.833 ; 100.053      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.898 ; 99.898       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.925 ; 99.925       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.136 ; 3.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.109 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.106 ; 3.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.104 ; 3.211 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.110 ; 3.217 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.107 ; 3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.136 ; 3.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.122 ; 3.229 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.121 ; 3.228 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.111 ; 3.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.121 ; 3.228 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 7.064 ; 7.472 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.152 ; 4.309 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.703 ; 4.991 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.917 ; 6.039 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.063 ; 5.289 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 7.064 ; 7.472 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.335 ; 6.599 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.323 ; 4.510 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.212 ; 4.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 6.335 ; 6.599 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.603 ; 5.795 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.190 ; 6.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.360 ; 6.665 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.537 ; 6.810 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.305 ; 4.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.106 ; -2.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.106 ; -2.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.106 ; -2.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.106 ; -2.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.116 ; -2.223 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.113 ; -2.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.111 ; -2.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.118 ; -2.225 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.114 ; -2.221 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.144 ; -2.251 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.130 ; -2.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.129 ; -2.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.119 ; -2.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.129 ; -2.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -3.077 ; -3.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.077 ; -3.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.605 ; -3.876 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.708 ; -4.778 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.872 ; -4.066 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.929 ; -4.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.857 ; -3.033 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.241 ; -3.413 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.073 ; -3.309 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -5.109 ; -5.315 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -4.411 ; -4.543 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.857 ; -3.033 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.188 ; -5.473 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.363 ; -5.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.223 ; -3.344 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.285 ; 3.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.212 ; 2.923 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.180 ; 2.891 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.188 ; 2.899 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.198 ; 2.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.285 ; 3.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.199 ; 2.910 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.209 ; 2.920 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.212 ; 2.923 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.299 ; 3.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.213 ; 2.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.299 ; 3.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.311 ; 3.854 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.223 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.357 ; 3.902 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.498 ; 3.187 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.498 ; 3.187 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.498 ; 3.187 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.354 ; 3.899 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.357 ; 3.902 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.287 ; 2.082 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.398 ; 3.101 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.422 ; 3.125 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.346 ; 3.891 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.494 ; 3.183 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.341 ; 3.886 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.485 ; 3.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.495 ; 3.184 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.369 ; 4.767 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.097 ; 3.346 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.369 ; 4.767 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.223 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.234 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.394 ; 8.769 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.428 ; 4.405 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.402 ; 3.172 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.555 ; 5.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.574 ; 3.834 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.672 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.431 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.064 ; 5.405 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.489 ; 2.452 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.064 ; 5.405 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.265 ; 2.208 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.047 ; 5.388 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.951 ; 5.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.951 ; 5.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.191 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.201 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.191 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.940 ; 5.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.181 ; 2.057 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.169 ; 2.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.179 ; 2.055 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.181 ; 2.057 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.171 ; 2.047 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.180 ; 2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.322 ; 2.038 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.353 ; 2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.343 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.343 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.343 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.322 ; 2.038 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.330 ; 2.046 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.339 ; 2.055 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.472 ; 3.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.341 ; 2.057 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.351 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.353 ; 2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.354 ; 2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.354 ; 2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.486 ; 3.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.498 ; 3.042 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.364 ; 2.080 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.476 ; 1.272 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.639 ; 2.334 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.639 ; 2.334 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.639 ; 2.334 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.543 ; 3.089 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.546 ; 3.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.476 ; 1.272 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.539 ; 2.248 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.562 ; 2.271 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.645 ; 2.340 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.536 ; 3.082 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.645 ; 2.340 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.645 ; 2.340 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.635 ; 2.330 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.531 ; 3.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.626 ; 2.321 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.636 ; 2.331 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.243 ; 2.488 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.243 ; 2.488 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.464 ; 3.853 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.364 ; 2.080 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.375 ; 2.091 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.456 ; 7.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.544 ; 3.521 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.546 ; 2.321 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 4.724 ; 5.000 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.707 ; 2.960 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.905 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.669 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.454 ; 1.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.679 ; 1.643 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.253 ; 4.595 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.454 ; 1.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.236 ; 4.578 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.378 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.139 ; 4.426 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.378 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.388 ; 1.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.378 ; 1.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.128 ; 4.415 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.357 ; 1.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.357 ; 1.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.367 ; 1.244 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.368 ; 1.245 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.358 ; 1.235 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.368 ; 1.245 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.476 ; 2.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.476 ; 2.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.476 ; 2.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.476 ; 2.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.892 ; 2.892 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.303 ; 3.303 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.267 ; 3.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.683 ; 3.683 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.658 ; 3.658 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.149 ; 4.149 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.757 ; 3.757 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.345 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.345 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.335 ; 3.335 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.329 ; 3.329 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.319 ; 3.319 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.329 ; 3.329 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.734 ; 3.350 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.705 ; 6.321 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 6.705 ; 6.321 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.153 ; 1.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.153 ; 1.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.153 ; 1.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.153 ; 1.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.553 ; 1.582 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.947 ; 1.976 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.913 ; 1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.312 ; 2.341 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.289 ; 2.318 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.760 ; 2.789 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.384 ; 2.413 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.988 ; 2.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.988 ; 2.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.978 ; 2.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.972 ; 2.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.962 ; 1.991 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.972 ; 2.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.768 ; 2.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.977 ; 5.609 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.977 ; 5.609 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.627     ; 2.867     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.003     ; 3.243     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.975     ; 3.215     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.361     ; 3.601     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.342     ; 3.582     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.820     ; 4.060     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.451     ; 3.691     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.070     ; 3.310     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.070     ; 3.310     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.060     ; 3.300     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.068     ; 3.308     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.058     ; 3.298     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.068     ; 3.308     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.252     ; 3.636     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.247     ; 6.631     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 6.247     ; 6.631     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.160     ; 1.160     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.160     ; 1.160     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.160     ; 1.160     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.160     ; 1.160     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.529     ; 1.529     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.889     ; 1.889     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.863     ; 1.863     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.233     ; 2.233     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.216     ; 2.216     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.675     ; 2.675     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.320     ; 2.320     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.955     ; 1.955     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.955     ; 1.955     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.945     ; 1.945     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.952     ; 1.952     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.942     ; 1.942     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.952     ; 1.952     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.306     ; 2.674     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.539     ; 5.907     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.539     ; 5.907     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 35.55 MHz  ; 35.55 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 76.47 MHz  ; 76.47 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 80.15 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
; 112.85 MHz ; 112.85 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 138.1 MHz  ; 138.1 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.697 ; -138.375      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.736 ; -1.736        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.432 ; -8.069        ;
; FPGA_CLK                                                                            ; -0.409 ; -0.409        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.931  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 5.262  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.680 ; -62.043       ;
; FPGA_CLK                                                                            ; -0.602 ; -0.602        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.382  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.404  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.600 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.557 ; -22.925       ;
; FPGA_CLK                                                                            ; -0.684 ; -17.784       ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.001  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.021  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.965 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.119 ; -3.082        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.443  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.256  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.266  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.841  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.571  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.715  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.509  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.345  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.224 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.455 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.697 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.345      ;
; -3.576 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.224      ;
; -3.528 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.176      ;
; -3.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.074      ;
; -3.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.059      ;
; -3.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.040      ;
; -3.387 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.035      ;
; -3.378 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 1.026      ;
; -3.263 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.921     ; 1.315      ;
; -3.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.921     ; 1.224      ;
; -3.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.326     ; 0.817      ;
; -3.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.326     ; 0.817      ;
; -3.149 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.325     ; 0.797      ;
; -3.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.921     ; 1.173      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.921     ; 1.072      ;
; -2.956 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.990      ;
; -2.956 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.990      ;
; -2.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.880     ; 0.988      ;
; -2.808 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.842      ;
; -2.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.817      ;
; -2.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.817      ;
; -2.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.817      ;
; -2.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.939     ; 0.817      ;
; -2.778 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.932     ; 0.819      ;
; -2.776 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.932     ; 0.817      ;
; -2.768 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.819      ;
; -2.767 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.818      ;
; -2.767 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.818      ;
; -2.767 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.818      ;
; -2.766 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.817      ;
; -2.756 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.807      ;
; -2.751 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.929     ; 0.795      ;
; -2.751 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.929     ; 0.795      ;
; -2.751 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.929     ; 0.795      ;
; -2.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.796      ;
; -2.744 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.795      ;
; -2.743 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.921     ; 0.795      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.880     ; 0.819      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.880     ; 0.819      ;
; -2.724 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.880     ; 0.817      ;
; -2.723 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.880     ; 0.816      ;
; -2.714 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.890     ; 0.797      ;
; -2.713 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.891     ; 0.795      ;
; -2.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.891     ; 0.794      ;
; -2.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.890     ; 0.795      ;
; -2.696 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.871     ; 0.798      ;
; -2.692 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.868     ; 0.797      ;
; 2.392  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 9.090      ;
; 2.440  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 9.042      ;
; 2.440  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 9.042      ;
; 2.499  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.964      ;
; 2.604  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.885      ;
; 2.653  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.839      ;
; 2.659  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.824      ;
; 2.659  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.824      ;
; 2.712  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.780      ;
; 2.712  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.780      ;
; 2.750  ; ram_do_reg[1]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.748      ;
; 2.769  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.717      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.773  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.710      ;
; 2.847  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.635      ;
; 2.874  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 8.615      ;
; 2.889  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.596      ;
; 2.898  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.593      ;
; 2.906  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.585      ;
; 2.910  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.573      ;
; 2.910  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.573      ;
; 2.958  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 8.520      ;
; 2.958  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 8.520      ;
; 2.960  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 8.528      ;
; 2.962  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.521      ;
; 2.962  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 8.521      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.978  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.503      ;
; 2.979  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.513      ;
; 2.985  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.497      ;
; 2.994  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 8.485      ;
; 2.994  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 8.485      ;
; 2.994  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 8.485      ;
; 3.011  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 8.477      ;
; 3.023  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[5]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.458      ;
; 3.023  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.458      ;
; 3.037  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 8.453      ;
; 3.047  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.435      ;
; 3.047  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.435      ;
; 3.047  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.435      ;
; 3.069  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.422      ;
; 3.070  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.422      ;
; 3.071  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 8.421      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.736 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.748     ; 1.238      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.494      ;
; -0.424 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.498      ;
; -0.413 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.487      ;
; -0.412 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.172      ; 1.485      ;
; -0.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.461      ;
; -0.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.451      ;
; -0.370 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.444      ;
; -0.369 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.443      ;
; -0.360 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.184      ; 1.445      ;
; -0.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.364      ;
; -0.295 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.358      ;
; -0.256 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.330      ;
; -0.255 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.317      ;
; -0.255 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.317      ;
; -0.254 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.316      ;
; -0.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.310      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.305      ;
; -0.240 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.314      ;
; -0.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.296      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.164      ; 1.234      ;
; -0.149 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.212      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.187      ;
; -0.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.184      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.174      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.170      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.184      ; 1.190      ;
; -0.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.166      ;
; -0.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.164      ;
; -0.088 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.151      ;
; -0.082 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.161      ; 1.144      ;
; -0.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.154      ;
; -0.079 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.185      ; 1.165      ;
; -0.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.185      ; 1.163      ;
; -0.069 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.132      ;
; -0.067 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.130      ;
; -0.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.185      ; 1.152      ;
; -0.062 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.136      ;
; -0.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.184      ; 1.146      ;
; -0.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.173      ; 1.125      ;
; -0.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.184      ; 1.132      ;
; 0.037  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.026      ;
; 3.878  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.759     ; 7.893      ;
; 4.173  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.759     ; 7.598      ;
; 5.373  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.414     ; 6.743      ;
; 6.879  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 5.250      ;
; 7.017  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 5.112      ;
; 7.099  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 5.030      ;
; 7.238  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.891      ;
; 7.406  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.723      ;
; 7.432  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.542      ; 6.529      ;
; 7.517  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 4.611      ;
; 7.518  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 4.610      ;
; 7.544  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.545      ; 6.420      ;
; 7.582  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.547      ;
; 7.623  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.542      ; 6.338      ;
; 7.630  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.499      ;
; 7.710  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.545      ; 6.254      ;
; 7.718  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.411      ;
; 7.734  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 4.394      ;
; 7.747  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 4.394      ;
; 7.747  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 4.394      ;
; 7.751  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.545      ; 6.213      ;
; 7.804  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.325      ;
; 7.855  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 4.273      ;
; 7.910  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.545      ; 6.054      ;
; 7.941  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.401     ; 4.188      ;
; 7.963  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 4.178      ;
; 8.015  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.542      ; 5.946      ;
; 8.084  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 4.057      ;
; 8.221  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 3.907      ;
; 8.277  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 3.864      ;
; 8.478  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 3.663      ;
; 8.698  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 3.430      ;
; 8.728  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.402     ; 3.400      ;
; 8.794  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.389     ; 3.347      ;
; 9.297  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.117     ; 1.004      ;
; 9.299  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.117     ; 1.002      ;
; 12.057 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 8.695      ;
; 12.198 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.095     ; 8.542      ;
; 12.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 8.542      ;
; 12.370 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.095     ; 8.370      ;
; 12.384 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.095     ; 8.356      ;
; 12.516 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 8.247      ;
; 12.518 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[3]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 8.245      ;
; 12.541 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.095     ; 8.199      ;
; 12.620 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.083     ; 8.132      ;
; 12.853 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.910      ;
; 13.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.753      ;
; 13.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.753      ;
; 13.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.753      ;
; 13.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.741      ;
; 13.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.741      ;
; 13.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.741      ;
; 13.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.654      ;
; 13.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.654      ;
; 13.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.654      ;
; 13.324 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.439      ;
; 13.324 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.439      ;
; 13.324 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.439      ;
; 13.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 7.333      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.409  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.162      ; 4.339      ;
; 93.762  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.860     ; 5.380      ;
; 96.226  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.668      ; 1.695      ;
; 196.789 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.144      ;
; 196.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.105      ;
; 196.875 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.058      ;
; 196.914 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.019      ;
; 196.915 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.018      ;
; 196.953 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.980      ;
; 196.954 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.979      ;
; 196.995 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.938      ;
; 196.997 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.936      ;
; 197.001 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.932      ;
; 197.040 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.893      ;
; 197.041 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.892      ;
; 197.041 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.892      ;
; 197.079 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.854      ;
; 197.080 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.853      ;
; 197.080 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.853      ;
; 197.108 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.825      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.812      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.810      ;
; 197.127 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.806      ;
; 197.130 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.803      ;
; 197.166 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.767      ;
; 197.166 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.767      ;
; 197.167 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.766      ;
; 197.167 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.766      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.728      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.728      ;
; 197.206 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.727      ;
; 197.206 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.727      ;
; 197.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.699      ;
; 197.245 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.688      ;
; 197.247 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.686      ;
; 197.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.684      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.680      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.680      ;
; 197.256 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.677      ;
; 197.292 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.641      ;
; 197.292 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.641      ;
; 197.293 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.640      ;
; 197.293 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.640      ;
; 197.295 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.638      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.602      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.602      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.601      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.601      ;
; 197.334 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.599      ;
; 197.360 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.573      ;
; 197.371 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.562      ;
; 197.373 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.560      ;
; 197.375 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.558      ;
; 197.376 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.557      ;
; 197.379 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.554      ;
; 197.379 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.554      ;
; 197.379 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.554      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.551      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.515      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.515      ;
; 197.419 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.419 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.419 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.421 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.512      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.476      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.476      ;
; 197.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.475      ;
; 197.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.475      ;
; 197.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.475      ;
; 197.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.473      ;
; 197.486 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.447      ;
; 197.497 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.436      ;
; 197.499 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.434      ;
; 197.501 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.432      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.431      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.431      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.429      ;
; 197.505 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.428      ;
; 197.505 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.428      ;
; 197.505 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.428      ;
; 197.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.425      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.388      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.389      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.389      ;
; 197.545 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.386      ;
; 197.545 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.388      ;
; 197.545 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.388      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.386      ;
; 197.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.350      ;
; 197.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.350      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.349      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.347      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.349      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.349      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.347      ;
; 197.612 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.321      ;
; 197.623 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.310      ;
; 197.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.308      ;
; 197.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.308      ;
; 197.626 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.305      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.931 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 4.584      ;
; 0.931 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 4.584      ;
; 0.951 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.565      ;
; 1.066 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 4.449      ;
; 1.066 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 4.449      ;
; 1.076 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.440      ;
; 1.216 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.300      ;
; 1.225 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.291      ;
; 1.351 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.165      ;
; 1.360 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 4.156      ;
; 1.388 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 4.129      ;
; 1.487 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 4.025      ;
; 1.523 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 3.994      ;
; 1.631 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.875      ;
; 1.698 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.830      ;
; 1.719 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.790      ;
; 1.742 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.787      ;
; 1.807 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.722      ;
; 1.823 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.705      ;
; 1.874 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.632      ;
; 1.874 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.633      ;
; 1.877 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.652      ;
; 1.900 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 3.623      ;
; 1.905 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.601      ;
; 1.937 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 3.601      ;
; 1.942 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.587      ;
; 2.002 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.661      ;
; 2.008 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.655      ;
; 2.071 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.437      ;
; 2.084 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.578      ;
; 2.085 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.577      ;
; 2.119 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.543      ;
; 2.120 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.542      ;
; 2.120 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.542      ;
; 2.146 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.360      ;
; 2.147 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.361      ;
; 2.158 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 3.349      ;
; 2.163 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.500      ;
; 2.164 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.499      ;
; 2.164 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.499      ;
; 2.165 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.498      ;
; 2.166 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.497      ;
; 2.167 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.496      ;
; 2.167 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.496      ;
; 2.278 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.385      ;
; 2.282 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 3.381      ;
; 2.300 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.355      ;
; 2.325 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.343      ;
; 2.325 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.343      ;
; 2.344 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.168      ;
; 2.366 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.289      ;
; 2.368 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.160      ;
; 2.389 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 3.271      ;
; 2.393 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.275      ;
; 2.393 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.275      ;
; 2.417 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 3.243      ;
; 2.417 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 3.243      ;
; 2.427 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 3.233      ;
; 2.438 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.230      ;
; 2.438 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.230      ;
; 2.439 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 3.232      ;
; 2.467 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 3.204      ;
; 2.473 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.185      ;
; 2.474 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.184      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.490 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.167      ;
; 2.493 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.165      ;
; 2.499 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.158      ;
; 2.500 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.157      ;
; 2.503 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.025      ;
; 2.531 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.137      ;
; 2.531 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.137      ;
; 2.531 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.137      ;
; 2.531 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 3.137      ;
; 2.534 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.123      ;
; 2.535 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.122      ;
; 2.535 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.122      ;
; 2.577 ; SDRAM_ADDR[0]                                                                             ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.079      ;
; 2.582 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.950      ;
; 2.601 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.926      ;
; 2.606 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.052      ;
; 2.629 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.029      ;
; 2.663 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 2.859      ;
; 2.669 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.748     ; 1.239      ;
; 2.713 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.945      ;
; 2.717 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.941      ;
; 2.724 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.804      ;
; 2.724 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.804      ;
; 2.724 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.804      ;
; 2.724 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.804      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 5.262  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.748     ; 1.583      ;
; 8.760  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 8.512      ;
; 8.857  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 8.415      ;
; 9.160  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.234     ; 8.013      ;
; 9.220  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 8.101      ;
; 9.497  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 7.772      ;
; 9.631  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 7.690      ;
; 9.777  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.185     ; 7.445      ;
; 9.883  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 7.437      ;
; 9.901  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 7.368      ;
; 9.946  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 7.373      ;
; 10.058 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.219     ; 7.130      ;
; 10.064 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 7.252      ;
; 10.119 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 7.201      ;
; 10.158 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 7.111      ;
; 10.158 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 7.160      ;
; 10.161 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 7.158      ;
; 10.163 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.124      ;
; 10.165 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 7.155      ;
; 10.180 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 7.136      ;
; 10.184 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 7.133      ;
; 10.217 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.070      ;
; 10.221 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 7.051      ;
; 10.237 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 7.081      ;
; 10.246 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.041      ;
; 10.277 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 6.944      ;
; 10.310 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 6.881      ;
; 10.326 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 6.946      ;
; 10.362 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 6.959      ;
; 10.371 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 6.916      ;
; 10.384 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 6.903      ;
; 10.396 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.123     ; 6.888      ;
; 10.414 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 6.905      ;
; 10.420 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.897      ;
; 10.435 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 6.785      ;
; 10.435 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.882      ;
; 10.438 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.117     ; 6.852      ;
; 10.439 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.877      ;
; 10.446 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 6.875      ;
; 10.506 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.810      ;
; 10.510 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.123     ; 6.774      ;
; 10.513 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 6.708      ;
; 10.524 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.793      ;
; 10.525 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.792      ;
; 10.535 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 6.785      ;
; 10.536 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 6.684      ;
; 10.542 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 6.778      ;
; 10.559 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.123     ; 6.725      ;
; 10.572 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 6.749      ;
; 10.599 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.717      ;
; 10.613 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.703      ;
; 10.623 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.695      ;
; 10.634 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 6.685      ;
; 10.674 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.185     ; 6.548      ;
; 10.703 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.614      ;
; 10.707 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 6.514      ;
; 10.718 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 6.601      ;
; 10.723 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 6.564      ;
; 10.724 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 6.596      ;
; 10.738 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 6.581      ;
; 10.758 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.402     ; 6.373      ;
; 10.780 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 6.489      ;
; 10.792 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.408     ; 6.333      ;
; 10.799 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.117     ; 6.491      ;
; 10.816 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.402     ; 6.315      ;
; 10.819 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.408     ; 6.306      ;
; 10.827 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.490      ;
; 10.843 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.474      ;
; 10.845 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.472      ;
; 10.852 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.466      ;
; 10.900 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.234     ; 6.273      ;
; 10.936 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 6.285      ;
; 11.003 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.314      ;
; 11.042 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.402     ; 6.089      ;
; 11.083 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.413     ; 6.037      ;
; 11.097 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.220      ;
; 11.101 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 6.219      ;
; 11.110 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.413     ; 6.010      ;
; 11.115 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 6.206      ;
; 11.127 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.117     ; 6.163      ;
; 11.185 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.410     ; 5.938      ;
; 11.195 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.123      ;
; 11.206 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 6.066      ;
; 11.296 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.022      ;
; 11.301 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 6.020      ;
; 11.314 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.199     ; 5.894      ;
; 11.321 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.996      ;
; 11.389 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 5.931      ;
; 11.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg                                                           ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 5.803      ;
; 11.459 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.410     ; 5.664      ;
; 11.469 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.803      ;
; 11.469 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.410     ; 5.654      ;
; 11.475 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 5.794      ;
; 11.496 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 5.773      ;
; 11.562 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 5.759      ;
; 11.572 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.700      ;
; 11.712 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.560      ;
; 12.051 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.408     ; 5.074      ;
; 12.129 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.406     ; 4.998      ;
; 12.156 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.402     ; 4.975      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                         ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.680 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 0.936      ;
; -1.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.337      ; 0.966      ;
; -1.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.337      ; 0.979      ;
; -1.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 0.967      ;
; -1.660 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.337      ; 0.980      ;
; -1.658 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 0.959      ;
; -1.653 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.336      ; 0.986      ;
; -1.641 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 0.975      ;
; -1.639 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 0.978      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.336      ; 1.001      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 0.981      ;
; -1.631 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 0.986      ;
; -1.617 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.315      ; 1.001      ;
; -1.607 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 1.009      ;
; -1.591 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 1.025      ;
; -1.585 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.043      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.047      ;
; -1.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 1.055      ;
; -1.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 1.058      ;
; -1.551 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.336      ; 1.088      ;
; -1.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.113      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.120      ;
; -1.489 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.139      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.129      ;
; -1.484 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.133      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.138      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.150      ;
; -1.472 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.145      ;
; -1.465 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.152      ;
; -1.445 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.313      ; 1.171      ;
; -1.442 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.316      ; 1.177      ;
; -1.436 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.181      ;
; -1.351 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.336      ; 1.288      ;
; -1.342 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.286      ;
; -1.340 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.288      ;
; -1.321 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.307      ;
; -1.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.298      ;
; -1.316 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.312      ;
; -1.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.326      ;
; -1.297 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.320      ;
; -1.294 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.314      ; 1.323      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[2]                                                                                                                                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[2]                                                                                                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                        ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                        ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.602 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.954      ; 3.713      ;
; 0.470  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.736      ;
; 0.470  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.736      ;
; 0.473  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.739      ;
; 0.694  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.960      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.962      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.698  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.963      ;
; 0.699  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.965      ;
; 0.700  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.966      ;
; 0.701  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.966      ;
; 0.701  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.967      ;
; 0.711  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.977      ;
; 0.714  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.979      ;
; 0.724  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.989      ;
; 1.014  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.281      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.281      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.280      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.281      ;
; 1.016  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.282      ;
; 1.016  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.282      ;
; 1.018  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.284      ;
; 1.018  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.283      ;
; 1.018  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.284      ;
; 1.019  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.019  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.285      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.021  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.021  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.021  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.021  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.286      ;
; 1.022  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.287      ;
; 1.023  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.289      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.296      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.295      ;
; 1.031  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.296      ;
; 1.031  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.297      ;
; 1.034  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.300      ;
; 1.035  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.301      ;
; 1.035  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.300      ;
; 1.035  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.301      ;
; 1.048  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.313      ;
; 1.115  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.381      ;
; 1.115  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.381      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.381      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.383      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.381      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.382      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.382      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.383      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.384      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.384      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.387      ;
; 1.120  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.386      ;
; 1.129  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.395      ;
; 1.135  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.402      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.403      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.402      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.403      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.402      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.403      ;
; 1.138  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.404      ;
; 1.140  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.406      ;
; 1.140  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.405      ;
; 1.140  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.406      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.408      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                      ; To Node                                                                                                                                                                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.035      ;
; 0.385 ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[3]                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.041      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_insn_fetch                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                     ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                     ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                               ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                               ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                               ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                               ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.469 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.735      ;
; 0.472 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.738      ;
; 0.494 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.759      ;
; 0.599 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.865      ;
; 0.602 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.867      ;
; 0.627 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.892      ;
; 0.656 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.921      ;
; 0.658 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.923      ;
; 0.685 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.692 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.694 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.959      ;
; 0.699 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.964      ;
; 0.702 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.968      ;
; 0.708 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.978      ;
; 0.723 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.988      ;
; 0.728 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.994      ;
; 0.801 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.066      ;
; 0.868 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.134      ;
; 0.880 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.145      ;
; 0.914 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.179      ;
; 0.933 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.198      ;
; 0.957 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.229      ;
; 0.969 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.973 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.245      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.244      ;
; 0.979 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.246      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.256      ;
; 0.999 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.264      ;
; 1.004 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.269      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.025 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.286      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.286      ;
; 1.049 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.314      ;
; 1.055 ; seq_reg[1]                                                ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.320      ;
; 1.057 ; seq_reg[1]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.322      ;
; 1.078 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.343      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.350      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.366      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.367      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.370      ;
; 1.128 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.394      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.395      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.395      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.398      ;
; 1.138 ; seq_reg[0]                                                ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.403      ;
; 1.140 ; seq_reg[0]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.405      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.411      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.411      ;
; 1.146 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.412      ;
; 1.147 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.413      ;
; 1.152 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.423      ;
; 1.154 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.419      ;
; 1.157 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.420      ;
; 1.158 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.421      ;
; 1.166 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.431      ;
; 1.166 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.431      ;
; 1.167 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.426      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                     ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.419 ; half_scandouble_enable_reg                                                    ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.684      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.740      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.740      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.740      ;
; 0.476 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.740      ;
; 0.610 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.875      ;
; 0.612 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.876      ;
; 0.612 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.877      ;
; 0.612 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.877      ;
; 0.613 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.877      ;
; 0.615 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.882      ;
; 0.622 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.887      ;
; 0.624 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.890      ;
; 0.624 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.889      ;
; 0.624 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.889      ;
; 0.646 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.913      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.648 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.914      ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.600 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.502     ; 0.989      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.557 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 3.620      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.546 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.165      ; 3.612      ;
; -2.349 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.159      ; 3.474      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
; -2.338 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.162      ; 3.466      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.150      ; 4.602      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.146      ; 4.598      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
; -0.684 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.147      ; 4.599      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                   ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                           ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.001 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.485      ;
; 8.002 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.479      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.004 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 3.473      ;
; 8.007 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.473      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.487      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.487      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.487      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.478      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.487      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.487      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.488      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.485      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.471      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.469      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.474      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.469      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.469      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.471      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.482      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[8]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[10]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.477      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.478      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.469      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.469      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.474      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.474      ;
; 8.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.475      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.485      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[25]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.485      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[10]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[17]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[6]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[4]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.483      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[7]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.482      ;
; 8.014 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.484      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                               ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.021 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.312      ;
; 8.021 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.311      ;
; 8.021 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.311      ;
; 8.022 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.310      ;
; 8.022 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.309      ;
; 8.022 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.309      ;
; 8.035 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.357     ; 3.130      ;
; 8.035 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.354     ; 3.133      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.114      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.114      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.376     ; 3.110      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.114      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.360     ; 3.126      ;
; 8.036 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.347     ; 3.139      ;
; 8.037 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.370     ; 3.115      ;
; 8.037 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.370     ; 3.115      ;
; 8.037 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.370     ; 3.115      ;
; 8.037 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.361     ; 3.124      ;
; 8.038 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.368     ; 3.116      ;
; 8.040 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.356     ; 3.126      ;
; 8.040 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.356     ; 3.126      ;
; 8.040 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.356     ; 3.126      ;
; 8.044 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.301      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.045 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.299      ;
; 8.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.237     ; 3.239      ;
; 8.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.234     ; 3.242      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.240     ; 3.235      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 3.248      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.256     ; 3.219      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.252     ; 3.223      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.252     ; 3.223      ;
; 8.058 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.252     ; 3.223      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 3.233      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.250     ; 3.224      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.250     ; 3.224      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.250     ; 3.224      ;
; 8.060 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.248     ; 3.225      ;
; 8.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.236     ; 3.235      ;
; 8.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.236     ; 3.235      ;
; 8.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.236     ; 3.235      ;
; 8.112 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.364      ;
; 8.112 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.372      ;
; 8.112 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.372      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.329      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.329      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.329      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.329      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.320      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.320      ;
; 8.276 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.069      ;
; 8.276 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.069      ;
; 8.276 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.069      ;
; 8.276 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.069      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.917      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 2.917      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.924      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.908      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.908      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.908      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.908      ;
; 8.570 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.908      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.913      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.913      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.913      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.913      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.902      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.903      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 2.904      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 2.904      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 2.904      ;
; 8.571 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.905      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.197     ; 5.245      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.197     ; 5.245      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 5.246      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 5.246      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 5.246      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.196     ; 5.246      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.197     ; 5.245      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.197     ; 5.245      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 5.247      ;
; 11.965 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 5.247      ;
; 11.991 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.244     ; 5.172      ;
; 11.991 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.244     ; 5.172      ;
; 12.019 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.229     ; 5.159      ;
; 12.020 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.226     ; 5.161      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.040 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.314      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 4.848      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.491 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.191     ; 4.850      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.492 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.192     ; 4.849      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
; 12.502 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 4.852      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.943      ; 4.185      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.119 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.940      ; 4.182      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
; -0.118 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.938      ; 4.181      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.443 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.317      ; 3.180      ;
; 0.456 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.313      ; 3.189      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.712 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.319      ; 3.334      ;
; 0.725 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.315      ; 3.343      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                  ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.256 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.627      ; 3.189      ;
; 2.256 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.627      ; 3.189      ;
; 2.256 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.627      ; 3.189      ;
; 2.256 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.627      ; 3.189      ;
; 2.260 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.622      ; 3.188      ;
; 2.260 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.622      ; 3.188      ;
; 2.260 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.622      ; 3.188      ;
; 2.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 3.343      ;
; 2.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 3.343      ;
; 2.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 3.343      ;
; 2.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 3.343      ;
; 2.523 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.624      ; 3.342      ;
; 2.523 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.624      ; 3.342      ;
; 2.523 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.624      ; 3.342      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.171      ; 3.181      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.175      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.175      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[24]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[30]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[30]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.175      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.175      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[29]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[31]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[31]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[31]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.177      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.175      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[25]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[27]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[23]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[20]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[22]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[22]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[21]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[21]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.166      ; 3.176      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[19]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.168      ; 3.178      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.704 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.169      ; 3.179      ;
; 2.705 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.173      ;
; 2.705 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.163      ; 3.174      ;
+-------+--------------------------------------------------------------------------------------+------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.266 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.728      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.728      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.728      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.728      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.726      ;
; 2.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.731      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.267 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.728      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.722      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.722      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 2.722      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 2.742      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.726      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.726      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.726      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.726      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.726      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.723      ;
; 2.268 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.721      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.733      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.733      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.733      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 2.736      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.733      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.724      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.721      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.721      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.727      ;
; 2.269 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.722      ;
; 2.270 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 2.737      ;
; 2.483 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.483 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.484 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.857      ;
; 2.484 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.857      ;
; 2.618 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.082      ;
; 2.618 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.073      ;
; 2.618 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.073      ;
; 2.618 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.082      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.083      ;
; 2.619 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 3.083      ;
; 2.661 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.117      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 3.126      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.841 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 4.304      ;
; 3.842 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.842 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.303      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.843 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.844 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.304      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
; 3.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 4.302      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.678 ; 5.833        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.679 ; 5.834        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.679 ; 5.834        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.715 ; 5.841        ; 0.126          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.795 ; 5.904        ; 0.109          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.841 ; 5.841        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.904 ; 5.904        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                             ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                    ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.345  ; 10.355       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                 ;
; 9.466  ; 10.476       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                 ;
; 10.070 ; 10.286       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                              ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                     ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_ena_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_ena_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_ena_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_ena_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_ena_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|areset_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                                                    ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_counter_state                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_init_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_ena_state                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reset_state                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|tmp_seq_ena_state                                                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                                                     ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[14]                                                              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                                              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                                                      ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]                                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]                                     ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]                                     ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.224 ; 17.606       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.242 ; 17.624       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ;
; 17.270 ; 17.486       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[1]                                                                                                         ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                         ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[1]                                                                                                              ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                              ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]      ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]          ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]        ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]            ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]            ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]       ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]       ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]      ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]         ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg                                                                                                                                             ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                            ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[0]                                                                                                           ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[1]                                                                                                           ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                           ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                      ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                              ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]            ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]       ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]      ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]      ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]      ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2] ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4] ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5] ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6] ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]          ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]          ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]     ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]     ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]     ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]     ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq          ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1]        ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]        ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]         ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]         ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]    ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]    ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]    ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]    ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]    ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq              ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                   ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                   ;
; 17.276 ; 17.492       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                   ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]      ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.592 ; 17.592       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.592 ; 17.592       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.592 ; 17.592       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.592 ; 17.592       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.592 ; 17.592       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.593 ; 17.593       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.648 ; 17.648       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.455 ; 99.555       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.332 ; 100.432      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.555 ; 99.555       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.623 ; 99.623       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.631 ; 99.631       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.914 ; 99.914       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.739 ; 2.846 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.713 ; 2.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.710 ; 2.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.707 ; 2.814 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.714 ; 2.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.710 ; 2.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.731 ; 2.838 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.739 ; 2.846 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.735 ; 2.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.735 ; 2.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.725 ; 2.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.723 ; 2.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.713 ; 2.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.723 ; 2.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 6.279 ; 6.875 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.619 ; 3.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.134 ; 4.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.306 ; 5.460 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.499 ; 4.769 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 6.279 ; 6.875 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.719 ; 6.053 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.798 ; 4.061 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.689 ; 4.022 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.719 ; 5.960 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.010 ; 5.198 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.473 ; 6.053 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.576 ; 5.756 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.744 ; 5.897 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.763 ; 4.005 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.832 ; -1.940 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.829 ; -1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.826 ; -1.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.833 ; -1.941 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.829 ; -1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.851 ; -1.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.859 ; -1.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.855 ; -1.963 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.855 ; -1.963 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.845 ; -1.953 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.842 ; -1.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.832 ; -1.940 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.842 ; -1.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.670 ; -2.920 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.670 ; -2.920 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.163 ; -3.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.231 ; -4.333 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.436 ; -3.679 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.476 ; -3.693 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.492 ; -2.731 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.843 ; -3.090 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.681 ; -2.982 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.628 ; -4.812 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.951 ; -4.086 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.492 ; -2.731 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.542 ; -4.710 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.707 ; -4.845 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.807 ; -3.034 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.223 ; 2.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.231 ; 2.995 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.240 ; 3.004 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.242 ; 3.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.252 ; 3.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.255 ; 3.019 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.520 ; 4.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.571 ; 4.123 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.571 ; 4.123 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.502 ; 2.304 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.435 ; 3.192 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.459 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.545 ; 3.288 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.561 ; 4.113 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.541 ; 3.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.541 ; 3.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.531 ; 3.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.558 ; 4.110 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.524 ; 3.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.534 ; 3.277 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.302 ; 4.911 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.190 ; 3.517 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.302 ; 4.911 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.275 ; 3.039 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.479 ; 8.651 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.597 ; 4.412 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.589 ; 3.276 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.754 ; 5.978 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.644 ; 3.993 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.973 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.699 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.277 ; 5.625 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.705 ; 2.675 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.277 ; 5.625 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.480 ; 2.430 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.262 ; 5.610 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.401 ; 2.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.411 ; 2.294 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.401 ; 2.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.151 ; 5.444 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.380 ; 2.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.390 ; 2.273 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.382 ; 2.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.391 ; 2.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.469 ; 2.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.500 ; 2.268 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.469 ; 2.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.478 ; 2.246 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.487 ; 2.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.781 ; 3.332 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.488 ; 2.256 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.498 ; 2.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.500 ; 2.268 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.501 ; 2.269 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.501 ; 2.269 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.794 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.805 ; 3.356 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.511 ; 2.279 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.789 ; 1.592 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.855 ; 3.408 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.858 ; 3.411 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.789 ; 1.592 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.680 ; 2.441 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.704 ; 2.465 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.791 ; 2.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.849 ; 3.402 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.787 ; 2.534 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.787 ; 2.534 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.777 ; 2.524 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.845 ; 3.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.769 ; 2.516 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.779 ; 2.526 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.438 ; 2.759 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.438 ; 2.759 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.506 ; 4.097 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.511 ; 2.279 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.521 ; 2.289 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.645 ; 7.825 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.815 ; 3.637 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.834 ; 2.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.022 ; 5.250 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.882 ; 3.222 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.301 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.032 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.767 ; 1.718 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.992 ; 1.963 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.564 ; 4.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.767 ; 1.718 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.549 ; 4.898 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.448 ; 4.742 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.697 ; 1.581 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.437 ; 4.731 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.666 ; 1.550 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.666 ; 1.550 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.676 ; 1.560 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.678 ; 1.562 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.668 ; 1.552 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.676 ; 1.560 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.314 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.314 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.314 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.314 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.704 ; 2.704 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.095 ; 3.095 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.065 ; 3.065 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.459 ; 3.459 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.438 ; 3.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.892 ; 3.892 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.522 ; 3.522 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.128 ; 3.128 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.128 ; 3.128 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.118 ; 3.118 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.113 ; 3.113 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.103 ; 3.103 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.113 ; 3.113 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.835 ; 3.459 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.603 ; 6.227 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 6.603 ; 6.227 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.297 ; 1.297 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.297 ; 1.297 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.297 ; 1.297 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.297 ; 1.297 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.672 ; 1.672 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.048 ; 2.048 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.018 ; 2.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.397 ; 2.397 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.377 ; 2.377 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.812 ; 2.812 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.458 ; 2.458 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.079 ; 2.079 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.079 ; 2.079 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.069 ; 2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.064 ; 2.064 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.054 ; 2.054 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.064 ; 2.064 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.974 ; 2.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.943 ; 5.582 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.943 ; 5.582 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.219     ; 2.290     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.219     ; 2.290     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.219     ; 2.290     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.219     ; 2.290     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.574     ; 2.645     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.927     ; 2.998     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.902     ; 2.973     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.256     ; 3.327     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.241     ; 3.312     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.682     ; 3.753     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.344     ; 3.415     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.986     ; 3.057     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.986     ; 3.057     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.976     ; 3.047     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.966     ; 3.037     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.956     ; 3.027     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.966     ; 3.037     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.292     ; 3.668     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.925     ; 6.301     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.925     ; 6.301     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.274     ; 1.410     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.274     ; 1.410     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.274     ; 1.410     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.274     ; 1.410     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.615     ; 1.751     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.954     ; 2.090     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.930     ; 2.066     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.270     ; 2.406     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.256     ; 2.392     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.679     ; 2.815     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.355     ; 2.491     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.011     ; 2.147     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.011     ; 2.147     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.001     ; 2.137     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.991     ; 2.127     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.981     ; 2.117     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.991     ; 2.127     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.453     ; 2.814     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.292     ; 5.653     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.292     ; 5.653     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.915 ; -75.110       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.158 ; -3.044        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -0.133 ; -0.133        ;
; FPGA_CLK                                                                            ; 0.435  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.419  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 7.070  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.055 ; -40.125       ;
; FPGA_CLK                                                                            ; -0.663 ; -0.663        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.144  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 11.408 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.240 ; -11.112       ;
; FPGA_CLK                                                                            ; 0.149  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.808  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.853  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.743 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.346 ; -8.996        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.033  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.085  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.132  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.888  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.801  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.560  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.381  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.475 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.268     ; 0.605      ;
; -1.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.268     ; 0.566      ;
; -1.854 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.543      ;
; -1.799 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.268     ; 0.489      ;
; -1.790 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.479      ;
; -1.787 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.476      ;
; -1.786 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.268     ; 0.476      ;
; -1.779 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.468      ;
; -1.734 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.598      ;
; -1.703 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.567      ;
; -1.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.385      ;
; -1.695 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.384      ;
; -1.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.374      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.547      ;
; -1.623 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.487      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.460      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.460      ;
; -1.583 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.460      ;
; -1.543 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.398      ;
; -1.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.385      ;
; -1.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.385      ;
; -1.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.385      ;
; -1.528 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.103     ; 0.383      ;
; -1.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.386      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.385      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.383      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.386      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.383      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.383      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.384      ;
; -1.514 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.378      ;
; -1.512 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.373      ;
; -1.511 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.372      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.373      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.371      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.386      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.386      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.373      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.371      ;
; -1.507 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.384      ;
; -1.507 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.375      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.383      ;
; -1.503 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.371      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.373      ;
; -1.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.371      ;
; -1.493 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.376      ;
; -1.490 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.374      ;
; 7.365  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.186      ;
; 7.395  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.156      ;
; 7.395  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.156      ;
; 7.453  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.098      ;
; 7.503  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.049      ;
; 7.503  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.049      ;
; 7.509  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 4.047      ;
; 7.516  ; ram_do_reg[1]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 4.039      ;
; 7.529  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 4.028      ;
; 7.529  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 4.028      ;
; 7.549  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.003      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.551  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 4.001      ;
; 7.557  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 4.000      ;
; 7.565  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 3.988      ;
; 7.581  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.970      ;
; 7.583  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.966      ;
; 7.585  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.970      ;
; 7.596  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 3.957      ;
; 7.596  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 3.957      ;
; 7.613  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.936      ;
; 7.627  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.929      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.630  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.920      ;
; 7.632  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 3.921      ;
; 7.632  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 3.921      ;
; 7.632  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.923      ;
; 7.641  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.914      ;
; 7.644  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.907      ;
; 7.656  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.895      ;
; 7.664  ; ram_do_reg[0]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.887      ;
; 7.667  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.103     ; 3.875      ;
; 7.667  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.103     ; 3.875      ;
; 7.674  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.103     ; 3.868      ;
; 7.674  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.103     ; 3.868      ;
; 7.674  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.103     ; 3.868      ;
; 7.677  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.879      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
; 7.690  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.861      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.671      ;
; -0.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.670      ;
; -0.150 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.663      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.665      ;
; -0.141 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.660      ;
; -0.136 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.655      ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.654      ;
; -0.132 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.658      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.638      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.639      ;
; -0.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.635      ;
; -0.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.634      ;
; -0.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.634      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.630      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.630      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.620      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.620      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.626      ;
; -0.095 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.608      ;
; -0.053 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.565      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.562      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.561      ;
; -0.046 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.559      ;
; -0.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.557      ;
; -0.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.557      ;
; -0.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.553      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.552      ;
; -0.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.546      ;
; -0.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.544      ;
; -0.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.550      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.555      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.555      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.552      ;
; -0.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.548      ;
; -0.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.533      ;
; -0.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.531      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.538      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.528      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.525      ;
; -0.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.530      ;
; 0.062  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.451      ;
; 7.862  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 3.395      ;
; 8.008  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 3.249      ;
; 8.285  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 3.153      ;
; 8.977  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.919      ; 3.346      ;
; 8.983  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.463      ;
; 9.030  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.919      ; 3.293      ;
; 9.057  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.389      ;
; 9.061  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.385      ;
; 9.065  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.920      ; 3.259      ;
; 9.103  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.920      ; 3.221      ;
; 9.124  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.920      ; 3.200      ;
; 9.135  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.311      ;
; 9.196  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.920      ; 3.128      ;
; 9.210  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.919      ; 3.113      ;
; 9.226  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.220      ;
; 9.257  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 2.188      ;
; 9.263  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 2.182      ;
; 9.307  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.139      ;
; 9.309  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.137      ;
; 9.342  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 2.112      ;
; 9.349  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 2.105      ;
; 9.360  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 2.085      ;
; 9.380  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.066      ;
; 9.388  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 2.058      ;
; 9.406  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 2.039      ;
; 9.445  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 2.009      ;
; 9.461  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.156     ; 1.985      ;
; 9.492  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 1.962      ;
; 9.566  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 1.879      ;
; 9.644  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.147     ; 1.811      ;
; 9.714  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 1.740      ;
; 9.792  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 1.653      ;
; 9.868  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.157     ; 1.577      ;
; 9.907  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.148     ; 1.547      ;
; 9.952  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.012     ; 0.439      ;
; 9.952  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.012     ; 0.439      ;
; 16.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.020     ; 5.549      ;
; 16.492 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.043     ; 4.285      ;
; 16.562 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.043     ; 4.215      ;
; 16.575 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.052     ; 4.193      ;
; 16.657 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.052     ; 4.111      ;
; 16.671 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.052     ; 4.097      ;
; 16.753 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.052     ; 4.015      ;
; 16.775 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.043     ; 4.002      ;
; 16.797 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.986      ;
; 16.804 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[3]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.979      ;
; 16.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.822      ;
; 17.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.657      ;
; 17.124 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.655      ;
; 17.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.640      ;
; 17.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.637      ;
; 17.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.635      ;
; 17.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.620      ;
; 17.250 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.534      ;
; 17.252 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.532      ;
; 17.267 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.517      ;
; 17.331 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[2]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.452      ;
; 17.336 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.448      ;
; 17.338 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.446      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -0.917     ; 0.521      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.435   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.773      ; 2.091      ;
; 96.858  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.688     ; 2.441      ;
; 98.690  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.597      ; 0.776      ;
; 198.372 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.581      ;
; 198.376 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.577      ;
; 198.440 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.513      ;
; 198.441 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.512      ;
; 198.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.509      ;
; 198.445 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.508      ;
; 198.455 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.498      ;
; 198.492 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.461      ;
; 198.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.445      ;
; 198.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.444      ;
; 198.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.444      ;
; 198.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.441      ;
; 198.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.440      ;
; 198.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.440      ;
; 198.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.430      ;
; 198.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.430      ;
; 198.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.394      ;
; 198.560 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.393      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.378      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.377      ;
; 198.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.376      ;
; 198.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.376      ;
; 198.579 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.374      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.373      ;
; 198.581 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.372      ;
; 198.581 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.372      ;
; 198.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.369      ;
; 198.591 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.362      ;
; 198.591 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.362      ;
; 198.621 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.332      ;
; 198.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.326      ;
; 198.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.325      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.310      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.309      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.308      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.308      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.308      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.306      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.305      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.304      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.304      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.304      ;
; 198.652 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.301      ;
; 198.659 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.294      ;
; 198.659 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.294      ;
; 198.659 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.294      ;
; 198.689 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.264      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.258      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.257      ;
; 198.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.256      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.242      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.241      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.241      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.240      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.240      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.240      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.238      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.237      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.237      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.236      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.236      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.236      ;
; 198.720 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.233      ;
; 198.727 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.226      ;
; 198.727 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.226      ;
; 198.727 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.226      ;
; 198.728 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.225      ;
; 198.757 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.196      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.190      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.189      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.189      ;
; 198.765 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.188      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.173      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.174      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.173      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.173      ;
; 198.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.172      ;
; 198.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.172      ;
; 198.781 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.172      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.169      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.169      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.170      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.169      ;
; 198.785 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.168      ;
; 198.785 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.168      ;
; 198.785 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.168      ;
; 198.788 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.165      ;
; 198.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.158      ;
; 198.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.158      ;
; 198.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.158      ;
; 198.796 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.157      ;
; 198.796 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.157      ;
; 198.825 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.128      ;
; 198.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.122      ;
; 198.832 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.121      ;
; 198.832 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.121      ;
; 198.832 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.034     ; 1.121      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.419 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.171      ;
; 3.419 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.171      ;
; 3.469 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.121      ;
; 3.469 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.121      ;
; 3.538 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.053      ;
; 3.547 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.043      ;
; 3.550 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.041      ;
; 3.588 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.003      ;
; 3.597 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 1.993      ;
; 3.605 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 1.986      ;
; 3.673 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.919      ;
; 3.697 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 1.884      ;
; 3.723 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.869      ;
; 3.727 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 1.861      ;
; 3.746 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 1.838      ;
; 3.771 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 1.811      ;
; 3.795 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 1.786      ;
; 3.818 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.778      ;
; 3.819 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.783      ;
; 3.860 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 1.721      ;
; 3.875 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.723      ;
; 3.875 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.721      ;
; 3.893 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.699      ;
; 3.905 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.751      ;
; 3.913 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.685      ;
; 3.925 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.673      ;
; 3.935 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.721      ;
; 3.938 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 1.644      ;
; 3.947 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.709      ;
; 3.949 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.707      ;
; 3.955 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 1.626      ;
; 3.963 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.635      ;
; 3.975 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 1.607      ;
; 3.976 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 1.606      ;
; 3.983 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.673      ;
; 3.983 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.673      ;
; 3.984 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.672      ;
; 3.986 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.670      ;
; 3.988 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.668      ;
; 3.988 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.668      ;
; 3.991 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.665      ;
; 3.991 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.665      ;
; 3.992 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.664      ;
; 3.992 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.664      ;
; 4.027 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.623      ;
; 4.034 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.616      ;
; 4.070 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.586      ;
; 4.072 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.584      ;
; 4.090 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 1.498      ;
; 4.126 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.531      ;
; 4.126 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.531      ;
; 4.129 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.467      ;
; 4.133 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.521      ;
; 4.144 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.510      ;
; 4.144 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.510      ;
; 4.147 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.510      ;
; 4.147 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.510      ;
; 4.155 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.498      ;
; 4.162 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.490      ;
; 4.167 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.485      ;
; 4.168 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.492      ;
; 4.170 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.486      ;
; 4.170 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.486      ;
; 4.170 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.482      ;
; 4.171 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.481      ;
; 4.173 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.479      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.174 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.179 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.417      ;
; 4.189 ; SDRAM_ADDR[0]                                                                             ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.462      ;
; 4.190 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.470      ;
; 4.207 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.445      ;
; 4.207 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.445      ;
; 4.208 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.449      ;
; 4.208 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.449      ;
; 4.208 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.449      ;
; 4.208 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.449      ;
; 4.208 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.444      ;
; 4.219 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.378      ;
; 4.239 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.413      ;
; 4.251 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.401      ;
; 4.256 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.336      ;
; 4.273 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.917     ; 0.521      ;
; 4.274 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 1.316      ;
; 4.283 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.370      ;
; 4.286 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.367      ;
; 4.286 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.301      ;
; 4.298 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.354      ;
; 4.302 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.350      ;
; 4.310 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.286      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.070  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -0.917     ; 0.661      ;
; 13.569 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 3.823      ;
; 13.605 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 3.787      ;
; 13.649 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 3.770      ;
; 13.711 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 3.622      ;
; 13.879 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 3.540      ;
; 13.881 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.111     ; 3.479      ;
; 13.907 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 3.483      ;
; 14.030 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.128     ; 3.313      ;
; 14.042 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.376      ;
; 14.052 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 3.338      ;
; 14.107 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.310      ;
; 14.118 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.299      ;
; 14.136 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.126     ; 3.209      ;
; 14.136 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 3.283      ;
; 14.142 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.273      ;
; 14.149 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 3.253      ;
; 14.162 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.256      ;
; 14.165 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 3.237      ;
; 14.167 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 3.192      ;
; 14.171 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.247      ;
; 14.178 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.238      ;
; 14.182 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.235      ;
; 14.195 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 3.207      ;
; 14.196 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.221      ;
; 14.197 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 3.195      ;
; 14.198 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 3.192      ;
; 14.201 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 3.218      ;
; 14.201 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.214      ;
; 14.230 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.071     ; 3.170      ;
; 14.263 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.153      ;
; 14.267 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 3.125      ;
; 14.268 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 3.134      ;
; 14.269 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.148      ;
; 14.271 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 3.131      ;
; 14.272 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.111     ; 3.088      ;
; 14.278 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.113     ; 3.080      ;
; 14.278 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 3.141      ;
; 14.286 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.067     ; 3.118      ;
; 14.289 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 3.070      ;
; 14.294 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.121      ;
; 14.297 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.071     ; 3.103      ;
; 14.307 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.109      ;
; 14.314 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.104      ;
; 14.322 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.094      ;
; 14.328 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.089      ;
; 14.334 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.071     ; 3.066      ;
; 14.347 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 3.012      ;
; 14.362 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.113     ; 2.996      ;
; 14.364 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.052      ;
; 14.373 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.045      ;
; 14.380 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.036      ;
; 14.380 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 3.038      ;
; 14.385 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.030      ;
; 14.389 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.026      ;
; 14.417 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.998      ;
; 14.421 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.138     ; 2.912      ;
; 14.426 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.991      ;
; 14.426 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.991      ;
; 14.427 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.989      ;
; 14.439 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.067     ; 2.965      ;
; 14.440 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 2.950      ;
; 14.448 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.954      ;
; 14.450 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.966      ;
; 14.451 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.966      ;
; 14.467 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.949      ;
; 14.474 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.943      ;
; 14.477 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 2.882      ;
; 14.490 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 2.816      ;
; 14.498 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.918      ;
; 14.501 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 2.918      ;
; 14.514 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 2.792      ;
; 14.523 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.117     ; 2.831      ;
; 14.530 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.215     ; 2.773      ;
; 14.530 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.215     ; 2.773      ;
; 14.541 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.876      ;
; 14.559 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 2.859      ;
; 14.560 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 2.832      ;
; 14.605 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.811      ;
; 14.608 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.809      ;
; 14.613 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg                                                           ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.748      ;
; 14.615 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 2.804      ;
; 14.617 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.799      ;
; 14.636 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.067     ; 2.768      ;
; 14.660 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 2.646      ;
; 14.676 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 2.624      ;
; 14.676 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 2.624      ;
; 14.677 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 2.713      ;
; 14.678 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 2.624      ;
; 14.689 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.081     ; 2.701      ;
; 14.705 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 2.714      ;
; 14.725 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 2.693      ;
; 14.732 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 2.660      ;
; 14.798 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 2.594      ;
; 14.848 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 2.454      ;
; 14.848 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 2.454      ;
; 14.872 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.079     ; 2.520      ;
; 15.040 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.118     ; 2.313      ;
; 15.054 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.067     ; 2.350      ;
; 15.066 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.116     ; 2.289      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.400      ;
; -1.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.422      ;
; -1.042 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.425      ;
; -1.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.427      ;
; -1.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.421      ;
; -1.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.429      ;
; -1.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.418      ;
; -1.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.433      ;
; -1.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.425      ;
; -1.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.428      ;
; -1.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.430      ;
; -1.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.433      ;
; -1.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.441      ;
; -1.016 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.439      ;
; -1.016 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.445      ;
; -1.014 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.440      ;
; -1.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.444      ;
; -1.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.445      ;
; -1.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.448      ;
; -1.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.462      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.482      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.488      ;
; -0.970 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.485      ;
; -0.967 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.488      ;
; -0.966 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.495      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.491      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.491      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.490      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.492      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.493      ;
; -0.956 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.499      ;
; -0.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.521      ;
; -0.909 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.558      ;
; -0.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.559      ;
; -0.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.563      ;
; -0.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.559      ;
; -0.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.567      ;
; -0.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.571      ;
; -0.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.568      ;
; -0.884 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.577      ;
; -0.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.576      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state            ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                        ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.663 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.208      ; 1.795      ;
; 0.194  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.313      ;
; 0.197  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.316      ;
; 0.206  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.325      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.308  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.427      ;
; 0.312  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.431      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.466  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.585      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.469  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.588      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.630      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.633      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.642      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.469      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.475      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.484      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.486      ;
; 0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.493      ;
; 0.172 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.495      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.182 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                                                                                                                 ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.505      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.507      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[1]                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; paddle_mode_reg                                                                                                                                                                                             ; paddle_mode_reg                                                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[14]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.196 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.208 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.328      ;
; 0.224 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.344      ;
; 0.253 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.280 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.400      ;
; 0.287 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.407      ;
; 0.291 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.411      ;
; 0.292 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.297 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.303 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
; 0.312 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.312 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.432      ;
; 0.351 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.471      ;
; 0.355 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.475      ;
; 0.378 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.498      ;
; 0.389 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.510      ;
; 0.408 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.528      ;
; 0.413 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.533      ;
; 0.428 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.554      ;
; 0.433 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.553      ;
; 0.435 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.555      ;
; 0.436 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.563      ;
; 0.436 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.557      ;
; 0.437 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.558      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; seq_reg[1]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; seq_reg[1]                                                ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.460 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.580      ;
; 0.464 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.584      ;
; 0.473 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 0.587      ;
; 0.473 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 0.587      ;
; 0.473 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.593      ;
; 0.497 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.617      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.515 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.029      ; 0.628      ;
; 0.516 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.635      ;
; 0.516 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.635      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.640      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.644      ;
; 0.525 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 0.639      ;
; 0.527 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.653      ;
; 0.539 ; seq_reg[0]                                                ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.659      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                     ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.192 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.314      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; half_scandouble_enable_reg                                                    ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.315      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.317      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.205 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.325      ;
; 0.261 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.038      ; 0.383      ;
; 0.261 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.383      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.381      ;
; 0.263 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.382      ;
; 0.265 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.386      ;
; 0.265 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.387      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.388      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
+-------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.408 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -0.783     ; 0.481      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.240 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.750      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.234 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.747      ;
; -1.115 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.688      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
; -1.109 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.685      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.764      ; 2.368      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.765      ; 2.369      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
; 0.149 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.766      ; 2.370      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                      ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.808  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.655      ;
; 9.809  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.143     ; 1.645      ;
; 9.809  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.648      ;
; 9.810  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.597      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 1.587      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.590      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.648      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.648      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.648      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.140     ; 1.646      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.141     ; 1.645      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.147     ; 1.639      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.147     ; 1.639      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.147     ; 1.639      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 1.640      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 1.640      ;
; 9.811  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 1.640      ;
; 9.812  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.122     ; 1.663      ;
; 9.812  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.145     ; 1.640      ;
; 9.812  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 1.634      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 1.581      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 1.581      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 1.582      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 1.582      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 1.582      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.590      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 1.587      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.590      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 1.581      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 1.588      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.590      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.664      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.122     ; 1.662      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.122     ; 1.662      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.121     ; 1.663      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.121     ; 1.663      ;
; 9.814  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 1.582      ;
; 9.814  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 1.576      ;
; 9.820  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.661      ;
; 9.820  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.661      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.660      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.660      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.660      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.660      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.662      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.714      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.714      ;
; 9.831  ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.708      ;
; 9.853  ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.689      ;
; 9.853  ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.689      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.688      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.688      ;
; 9.857  ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.682      ;
; 9.857  ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.682      ;
; 9.938  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.545      ;
; 9.938  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.545      ;
; 9.938  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.545      ;
; 9.938  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.545      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.498      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.504      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.494      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.494      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.494      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.497      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.494      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.487      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.487      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.487      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.488      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.491      ;
; 10.050 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.492      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.494      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.494      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.494      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.494      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.493      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.493      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.493      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.493      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.486      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.492      ;
; 10.051 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.492      ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                               ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.853 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.691      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.698      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.102     ; 1.687      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.688      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.102     ; 1.687      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.102     ; 1.687      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.688      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.690      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.691      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack1                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.wr                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.slv_ack2                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.692      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.102     ; 1.687      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.102     ; 1.687      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.688      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.688      ;
; 9.856 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.689      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.698      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.698      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.698      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.694      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.698      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.698      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.699      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.696      ;
; 9.859 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.688      ;
; 9.859 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.101     ; 1.685      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.697      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.696      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
; 9.860 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.694      ;
+-------+---------------------------------------+-----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 14.743 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.140     ; 2.588      ;
; 14.743 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.140     ; 2.588      ;
; 14.757 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.130     ; 2.584      ;
; 14.759 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.128     ; 2.584      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.114     ; 2.594      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.114     ; 2.594      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.114     ; 2.594      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.113     ; 2.595      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.113     ; 2.595      ;
; 14.764 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.114     ; 2.593      ;
; 14.764 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.115     ; 2.592      ;
; 14.764 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.114     ; 2.593      ;
; 14.764 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.115     ; 2.592      ;
; 14.764 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.115     ; 2.592      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.773 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.648      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.420      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.104     ; 2.422      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.421      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
; 14.996 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.425      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.200      ; 2.104      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.201      ; 2.105      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
; -0.346 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.202      ; 2.106      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.261      ; 1.603      ;
; 0.042 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.257      ; 1.608      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 1.670      ;
; 0.223 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.260      ; 1.675      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.085 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.360      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.360      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.360      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.360      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.358      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.363      ;
; 1.085 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.367      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.355      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.362      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.360      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.073      ; 1.352      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.357      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.358      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.354      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.353      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.362      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.358      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.358      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.358      ;
; 1.176 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.414      ;
; 1.176 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.414      ;
; 1.176 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.414      ;
; 1.176 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.414      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.531      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.528      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.531      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.528      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.531      ;
; 1.259 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.531      ;
; 1.273 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.545      ;
; 1.273 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.545      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                    ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.132 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.278      ; 1.605      ;
; 1.132 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.278      ; 1.605      ;
; 1.132 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.278      ; 1.605      ;
; 1.133 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.280      ; 1.608      ;
; 1.133 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.280      ; 1.608      ;
; 1.133 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.280      ; 1.608      ;
; 1.133 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.280      ; 1.608      ;
; 1.307 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.281      ; 1.672      ;
; 1.307 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.281      ; 1.672      ;
; 1.307 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.281      ; 1.672      ;
; 1.308 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_busy_reg                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 1.675      ;
; 1.308 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 1.675      ;
; 1.308 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 1.675      ;
; 1.308 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.283      ; 1.675      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.607      ;
; 1.318 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.090      ; 1.604      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.085      ; 1.599      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.085      ; 1.599      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.598      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.085      ; 1.599      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.598      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.085      ; 1.599      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.603      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.603      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.598      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.603      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.603      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[30]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[31]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.598      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.608      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.086      ; 1.600      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.087      ; 1.601      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.086      ; 1.600      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.088      ; 1.602      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.607      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.607      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.086      ; 1.600      ;
; 1.319 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.086      ; 1.600      ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.167      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.085      ; 2.168      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 2.167      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
; 1.895 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.077      ; 2.166      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[7]                   ;
; 5.664 ; 5.819        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[4]                   ;
; 5.664 ; 5.819        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.801 ; 5.870        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.823 ; 5.876        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.870 ; 5.870        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.876 ; 5.876        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                            ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                       ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_address_reg0 ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                                                                                                         ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                                                                                   ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                                                                                    ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                        ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                        ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                        ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                                        ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                        ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127]                                                                                ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                                                                                ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                                                                                                 ;
; 8.594 ; 8.810        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                                                                                                 ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.381  ; 10.391       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 9.431  ; 10.441       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.183 ; 10.399       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                                                                   ;
; 10.183 ; 10.399       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                                                                   ;
; 10.197 ; 10.381       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_ena_state                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_ena_state                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_ena_state                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_ena_state                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInSyncReg2[0]                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInSyncReg2[1]                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~_Duplicate_1                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~_Duplicate_1                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[3]                                                             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a33~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a32~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a35~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a39~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_we_reg                         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_we_reg                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                        ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0                    ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~portb_address_reg0                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_datain_reg0                  ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~portb_address_reg0                 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 17.391 ; 17.607       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[13]                                                                                                                                                                                                                                   ;
; 17.391 ; 17.607       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[6]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[10]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[15]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[16]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[17]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[18]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[19]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[20]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[3]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[4]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[7]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[8]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[9]                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.616 ; 17.616       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.475  ; 99.575       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.319  ; 100.419      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.452  ; 99.452       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.552  ; 99.552       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.557  ; 99.557       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.575  ; 99.575       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.534 ; 2.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.501 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.501 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.501 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.513 ; 2.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.516 ; 2.074 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.513 ; 2.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.514 ; 2.072 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.517 ; 2.075 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.528 ; 2.086 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.534 ; 2.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.530 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.530 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.520 ; 2.078 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.519 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.509 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.519 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 3.396 ; 3.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.053 ; 2.521 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 2.319 ; 2.793 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.787 ; 3.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.444 ; 2.965 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.396 ; 3.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 2.998 ; 3.551 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.153 ; 2.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.051 ; 2.573 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.908 ; 3.551 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.658 ; 3.206 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 2.998 ; 3.434 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.080 ; 3.857 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.147 ; 3.912 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 2.158 ; 2.619 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.052 ; -1.610 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.050 ; -1.608 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.053 ; -1.611 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.064 ; -1.622 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.071 ; -1.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.056 ; -1.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.045 ; -1.603 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.550 ; -2.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.550 ; -2.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.808 ; -2.278 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.231 ; -2.740 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.894 ; -2.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.923 ; -2.397 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.437 ; -1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.647 ; -2.108 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.522 ; -2.037 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.346 ; -2.961 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.105 ; -2.626 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.437 ; -1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.535 ; -3.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.599 ; -3.350 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.653 ; -2.111 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.545 ; 2.251 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.577 ; 1.426 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.553 ; 1.402 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.561 ; 1.410 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.570 ; 1.419 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.545 ; 2.251 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.572 ; 1.421 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.582 ; 1.431 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.577 ; 1.426 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.552 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.579 ; 1.428 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.552 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.564 ; 2.270 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.589 ; 1.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.598 ; 2.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.598 ; 2.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.595 ; 2.317 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.137 ; 1.049 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.654 ; 1.504 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.671 ; 1.521 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.737 ; 1.591 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.596 ; 2.318 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.735 ; 1.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.735 ; 1.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.592 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.716 ; 1.570 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.726 ; 1.580 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.175 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.519 ; 1.524 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.175 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.589 ; 1.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.599 ; 1.448 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 4.339 ; 5.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.083 ; 2.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.505 ; 1.562 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.046 ; 3.551 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.793 ; 1.711 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.019 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.963 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.880 ; 3.348 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.264 ; 1.283 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.880 ; 3.348 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.084 ; 1.146 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.870 ; 3.338 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.833 ; 3.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.833 ; 3.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.056 ; 1.022 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.066 ; 1.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.056 ; 1.022 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.821 ; 3.254 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.047 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.034 ; 1.000 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.044 ; 1.010 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.047 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.037 ; 1.003 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.045 ; 1.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.145 ; 0.996 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.155 ; 1.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.152 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.156 ; 1.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.166 ; 1.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.158 ; 1.864 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.170 ; 1.876 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.744 ; 0.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.205 ; 1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.202 ; 1.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.744 ; 0.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.237 ; 1.089 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.254 ; 1.106 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.320 ; 1.176 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.204 ; 1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.199 ; 1.921 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.299 ; 1.155 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.309 ; 1.165 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.106 ; 1.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.106 ; 1.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.737 ; 1.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.183 ; 1.034 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.892 ; 4.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.661 ; 1.839 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.097 ; 1.151 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.646 ; 3.149 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.373 ; 1.295 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.649 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.593 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.691 ; 0.753 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.871 ; 0.890 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.487 ; 2.955 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.691 ; 0.753 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.477 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.439 ; 2.872 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.672 ; 0.638 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.428 ; 2.861 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.651 ; 0.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.653 ; 0.619 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.643 ; 0.609 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.652 ; 0.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.885 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.885 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.885 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.885 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.075 ; 2.048 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.251 ; 2.224 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.241 ; 2.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.427 ; 2.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.427 ; 2.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.649 ; 2.622 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.469 ; 2.442 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.289 ; 2.262 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.289 ; 2.262 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.279 ; 2.252 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.270 ; 2.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.260 ; 2.233 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.270 ; 2.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.817 ; 2.441 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.145 ; 3.769 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 4.145 ; 3.769 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.596 ; 0.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.596 ; 0.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.596 ; 0.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.596 ; 0.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.780 ; 0.780 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 0.948 ; 0.948 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.938 ; 0.938 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.117 ; 1.117 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.117 ; 1.117 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.331 ; 1.331 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.158 ; 1.158 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.985 ; 0.985 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.985 ; 0.985 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.975 ; 0.975 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.967 ; 0.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.957 ; 0.957 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.967 ; 0.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.303 ; 1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.750 ; 3.389 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.750 ; 3.389 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.925     ; 1.925     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.925     ; 1.925     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.925     ; 1.925     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.925     ; 1.925     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.130     ; 2.130     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.329     ; 2.329     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.315     ; 2.315     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.516     ; 2.516     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.513     ; 2.513     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.778     ; 2.778     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.585     ; 2.585     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.379     ; 2.379     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.379     ; 2.379     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.369     ; 2.369     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.362     ; 2.362     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.352     ; 2.352     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.362     ; 2.362     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.537     ; 2.913     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.943     ; 4.319     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.943     ; 4.319     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.634     ; 0.751     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.634     ; 0.751     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.634     ; 0.751     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.634     ; 0.751     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 0.832     ; 0.949     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.023     ; 1.140     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.010     ; 1.127     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.203     ; 1.320     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.199     ; 1.316     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.455     ; 1.572     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.269     ; 1.386     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.071     ; 1.188     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.071     ; 1.188     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.061     ; 1.178     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.054     ; 1.171     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.044     ; 1.161     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.054     ; 1.171     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.034     ; 2.395     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.557     ; 3.918     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.557     ; 3.918     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                  ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Clock                                                                                ; Setup    ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Worst-case Slack                                                                     ; -4.085   ; -1.935  ; -2.760   ; -0.346  ; 5.568               ;
;  FPGA_CLK                                                                            ; -0.409   ; -0.788  ; -0.684   ; -0.346  ; 89.418              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.601    ; 0.186   ; 7.639    ; 1.085   ; 5.568               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.085   ; 0.144   ; 7.634    ; 1.132   ; 17.188              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.027   ; 11.408  ; N/A      ; N/A     ; 5.696               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.958    ; 0.187   ; 11.557   ; 1.888   ; 8.506               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 17.588              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.432   ; -1.935  ; -2.760   ; 0.033   ; 9.345               ;
; Design-wide TNS                                                                      ; -164.864 ; -72.25  ; -40.717  ; -8.996  ; 0.0                 ;
;  FPGA_CLK                                                                            ; -0.409   ; -0.788  ; -17.784  ; -8.996  ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -156.488 ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.027   ; 0.000   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -8.069   ; -71.462 ; -24.728  ; 0.000   ; 0.000               ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.136 ; 3.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.098 ; 3.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.109 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.106 ; 3.213 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.104 ; 3.211 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.110 ; 3.217 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.107 ; 3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.136 ; 3.243 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.132 ; 3.239 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.122 ; 3.229 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.121 ; 3.228 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.111 ; 3.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.121 ; 3.228 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 7.064 ; 7.472 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.152 ; 4.309 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.703 ; 4.991 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.917 ; 6.039 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.063 ; 5.289 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 7.064 ; 7.472 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.335 ; 6.599 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.323 ; 4.510 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.212 ; 4.476 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 6.335 ; 6.599 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.603 ; 5.795 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.190 ; 6.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.360 ; 6.665 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.537 ; 6.810 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.305 ; 4.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.052 ; -1.610 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.050 ; -1.608 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.053 ; -1.611 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.064 ; -1.622 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.071 ; -1.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.056 ; -1.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.045 ; -1.603 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.550 ; -2.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.550 ; -2.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.808 ; -2.278 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.231 ; -2.740 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.894 ; -2.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.923 ; -2.397 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.437 ; -1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.647 ; -2.108 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.522 ; -2.037 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.346 ; -2.961 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.105 ; -2.626 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.437 ; -1.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.535 ; -3.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.599 ; -3.350 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.653 ; -2.111 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.223 ; 2.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.231 ; 2.995 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.240 ; 3.004 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.242 ; 3.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.252 ; 3.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.255 ; 3.019 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.520 ; 4.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.571 ; 4.123 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.571 ; 4.123 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.502 ; 2.304 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.435 ; 3.192 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.459 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.545 ; 3.288 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.561 ; 4.113 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.541 ; 3.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.541 ; 3.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.531 ; 3.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.558 ; 4.110 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.524 ; 3.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.534 ; 3.277 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.369 ; 4.911 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.190 ; 3.517 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.369 ; 4.911 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.275 ; 3.039 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 8.479 ; 8.769 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.597 ; 4.412 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.589 ; 3.276 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.754 ; 5.978 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.644 ; 3.993 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.973 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.699 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.277 ; 5.625 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.705 ; 2.675 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.277 ; 5.625 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.480 ; 2.430 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.262 ; 5.610 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.401 ; 2.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.411 ; 2.294 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.401 ; 2.284 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.151 ; 5.444 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.380 ; 2.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.390 ; 2.273 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.382 ; 2.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.391 ; 2.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.145 ; 0.996 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.155 ; 1.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.152 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.156 ; 1.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.166 ; 1.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.158 ; 1.864 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.170 ; 1.876 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.744 ; 0.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.307 ; 1.163 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.205 ; 1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.202 ; 1.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.744 ; 0.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.237 ; 1.089 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.254 ; 1.106 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.320 ; 1.176 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.204 ; 1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.199 ; 1.921 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.299 ; 1.155 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.309 ; 1.165 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.106 ; 1.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.106 ; 1.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.737 ; 1.656 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.183 ; 1.034 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.892 ; 4.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.661 ; 1.839 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.097 ; 1.151 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.646 ; 3.149 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.373 ; 1.295 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.649 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.593 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.691 ; 0.753 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.871 ; 0.890 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.487 ; 2.955 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.691 ; 0.753 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.477 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.439 ; 2.872 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.672 ; 0.638 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.662 ; 0.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.428 ; 2.861 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.651 ; 0.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.653 ; 0.619 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.643 ; 0.609 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.652 ; 0.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_P         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; USB2_P       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; USB2_N       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10687    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11727655 ; 0        ; 102056   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 47       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 315      ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1656     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 41       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 12209    ; 7        ; 43       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10687    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11727655 ; 0        ; 102056   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 47       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 315      ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1656     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 41       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 12209    ; 7        ; 43       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5209     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 176      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5209     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 176      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 31    ; 31   ;
; Unconstrained Input Port Paths  ; 63    ; 63   ;
; Unconstrained Output Ports      ; 57    ; 57   ;
; Unconstrained Output Port Paths ; 77    ; 77   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun May 31 21:28:06 2020
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] could not be matched with a clock
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.085
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.085      -156.488 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -2.027        -2.027 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.348        -6.231 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.118        -0.118 FPGA_CLK 
    Info (332119):     0.601         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.958         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.935
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.935       -71.462 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.788        -0.788 FPGA_CLK 
    Info (332119):     0.406         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.454         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.872         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.760
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.760       -24.728 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.615       -15.989 FPGA_CLK 
    Info (332119):     7.634         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.639         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.557         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.271
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.271        -6.996 FPGA_CLK 
    Info (332119):     0.454         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.538         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.539         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.287         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.568
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.568         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.696         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.506         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.346         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.188         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.588         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.418         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.697
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.697      -138.375 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.736        -1.736 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.432        -8.069 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.409        -0.409 FPGA_CLK 
    Info (332119):     0.931         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.262         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.680
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.680       -62.043 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.602        -0.602 FPGA_CLK 
    Info (332119):     0.382         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.403         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.404         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.600         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.557
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.557       -22.925 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.684       -17.784 FPGA_CLK 
    Info (332119):     8.001         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.021         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.965         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.119
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.119        -3.082 FPGA_CLK 
    Info (332119):     0.443         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.256         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.266         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.841         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.571
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.571         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.715         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.509         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.345         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.224         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.455         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.915
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.915       -75.110 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.158        -3.044 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.133        -0.133 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.435         0.000 FPGA_CLK 
    Info (332119):     3.419         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.070         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.055
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.055       -40.125 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.663        -0.663 FPGA_CLK 
    Info (332119):     0.144         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    11.408         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.240
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.240       -11.112 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.149         0.000 FPGA_CLK 
    Info (332119):     9.808         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.853         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    14.743         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.346
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.346        -8.996 FPGA_CLK 
    Info (332119):     0.033         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.085         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.132         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.888         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.655
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.655         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.801         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.560         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.381         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.475         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 575 megabytes
    Info: Processing ended: Sun May 31 21:28:16 2020
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:12


