TimeQuest Timing Analyzer report for atari800core
Mon Nov 11 22:22:55 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'FPGA_CLK'
 27. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'FPGA_CLK'
 31. Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Output Enable Times
 47. Minimum Output Enable Times
 48. Output Disable Times
 49. Minimum Output Disable Times
 50. Slow 1200mV 85C Model Metastability Report
 51. Slow 1200mV 0C Model Fmax Summary
 52. Slow 1200mV 0C Model Setup Summary
 53. Slow 1200mV 0C Model Hold Summary
 54. Slow 1200mV 0C Model Recovery Summary
 55. Slow 1200mV 0C Model Removal Summary
 56. Slow 1200mV 0C Model Minimum Pulse Width Summary
 57. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 58. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 59. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 61. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 65. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 69. Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Recovery: 'FPGA_CLK'
 71. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 74. Slow 1200mV 0C Model Removal: 'FPGA_CLK'
 75. Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 78. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 80. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 81. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 86. Setup Times
 87. Hold Times
 88. Clock to Output Times
 89. Minimum Clock to Output Times
 90. Output Enable Times
 91. Minimum Output Enable Times
 92. Output Disable Times
 93. Minimum Output Disable Times
 94. Slow 1200mV 0C Model Metastability Report
 95. Fast 1200mV 0C Model Setup Summary
 96. Fast 1200mV 0C Model Hold Summary
 97. Fast 1200mV 0C Model Recovery Summary
 98. Fast 1200mV 0C Model Removal Summary
 99. Fast 1200mV 0C Model Minimum Pulse Width Summary
100. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
103. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
104. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
106. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
108. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
111. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
112. Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
113. Fast 1200mV 0C Model Recovery: 'FPGA_CLK'
114. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
115. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
116. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
117. Fast 1200mV 0C Model Removal: 'FPGA_CLK'
118. Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
119. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
120. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
121. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
122. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
123. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
124. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
125. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
126. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
127. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
129. Setup Times
130. Hold Times
131. Clock to Output Times
132. Minimum Clock to Output Times
133. Output Enable Times
134. Minimum Output Enable Times
135. Output Disable Times
136. Minimum Output Disable Times
137. Fast 1200mV 0C Model Metastability Report
138. Multicorner Timing Analysis Summary
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Board Trace Model Assignments
144. Input Transition Times
145. Signal Integrity Metrics (Slow 1200mv 0c Model)
146. Signal Integrity Metrics (Slow 1200mv 85c Model)
147. Signal Integrity Metrics (Fast 1200mv 0c Model)
148. Setup Transfers
149. Hold Transfers
150. Recovery Transfers
151. Removal Transfers
152. Report TCCS
153. Report RSKM
154. Unconstrained Paths
155. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone IV E                                                      ;
; Device Name        ; EP4CE15E22C7                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.56        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-3         ;  22.2%      ;
;     Processor 4            ;  11.1%      ;
;     Processors 5-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Mon Nov 11 22:22:47 2019 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Clock Name                                                                          ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                             ; Source                                                                                ; Targets                                                                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                            ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                    ;                                                                                       ; { FPGA_CLK }                                                                            ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                 ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 36.49 MHz  ; 36.49 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 99.87 MHz  ; 99.87 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 103.92 MHz ; 100.0 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; limit due to minimum period restriction (tmin) ;
; 142.11 MHz ; 142.11 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 209.29 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                          ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.639 ; -274.407      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675 ; -1.675        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.298 ; -10.605       ;
; FPGA_CLK                                                                            ; 0.214  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.022  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 2.773  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.823 ; -130.025      ;
; FPGA_CLK                                                                            ; -0.824 ; -0.824        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.339  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.412  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.414  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.635 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                       ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.376 ; -21.384       ;
; FPGA_CLK                                                                            ; -0.325 ; -8.425        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.625  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.963  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.961 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.334 ; -8.634        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.337  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.480  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.256  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.680  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.600  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.720  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.535  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.374  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.259 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.595 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.530 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.639 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 1.195      ;
; -3.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 1.146      ;
; -3.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 1.015      ;
; -3.448 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 1.004      ;
; -3.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 0.986      ;
; -3.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 0.982      ;
; -3.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.973      ;
; -3.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.427     ; 0.934      ;
; -3.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.941      ;
; -3.384 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.939      ;
; -3.260 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.438     ; 0.791      ;
; -3.259 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.438     ; 0.790      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.426     ; 0.791      ;
; -3.246 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.426     ; 0.789      ;
; -3.234 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.789      ;
; -3.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.413     ; 0.789      ;
; -3.216 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.026     ; 1.159      ;
; -3.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 1.145      ;
; -3.176 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.014     ; 1.131      ;
; -3.087 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.999      ;
; -3.065 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.977      ;
; -3.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.977      ;
; -3.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 1.017      ;
; -3.058 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.975      ;
; -3.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 1.013      ;
; -3.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 1.010      ;
; -3.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.010     ; 1.010      ;
; -3.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.010     ; 1.010      ;
; -3.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.026     ; 0.991      ;
; -3.042 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 1.000      ;
; -3.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.010     ; 0.985      ;
; -3.023 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.981      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.976      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.026     ; 0.963      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.978      ;
; -3.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.976      ;
; -3.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.010     ; 0.970      ;
; -3.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.968      ;
; -3.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.962      ;
; -3.003 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.014     ; 0.958      ;
; -2.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.014     ; 0.953      ;
; -2.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.014     ; 0.930      ;
; -2.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.014     ; 0.923      ;
; -2.923 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.835      ;
; -2.922 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.839      ;
; -2.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.835      ;
; -2.917 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.834      ;
; -2.913 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.825      ;
; -2.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.814      ;
; -2.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.814      ;
; -2.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.057     ; 0.814      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.054     ; 0.816      ;
; -2.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.813      ;
; -2.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.055     ; 0.813      ;
; -2.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.814      ;
; -2.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.054     ; 0.812      ;
; -2.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.052     ; 0.813      ;
; -2.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.815      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.813      ;
; -2.891 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.812      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.044     ; 0.814      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.044     ; 0.814      ;
; -2.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.044     ; 0.812      ;
; -2.886 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.042     ; 0.813      ;
; -2.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.042     ; 0.812      ;
; -2.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.042     ; 0.812      ;
; -2.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.837      ;
; -2.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.837      ;
; -2.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.837      ;
; -2.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.835      ;
; -2.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.834      ;
; -2.868 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.789      ;
; -2.867 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.788      ;
; -2.864 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.044     ; 0.789      ;
; -2.863 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.043     ; 0.789      ;
; -2.862 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.042     ; 0.789      ;
; -2.858 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.814      ;
; -2.854 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.812      ;
; -2.854 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.812      ;
; -2.852 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.033     ; 0.788      ;
; -2.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.836      ;
; -2.848 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.834      ;
; -2.848 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.834      ;
; -2.845 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.979     ; 0.835      ;
; -2.845 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.025     ; 0.789      ;
; -2.844 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.025     ; 0.788      ;
; -2.835 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.791      ;
; -2.833 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.013     ; 0.789      ;
; -2.831 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.011     ; 0.789      ;
; -2.827 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.813      ;
; -2.822 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.979     ; 0.812      ;
; 1.892  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.594      ;
; 2.071  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.415      ;
; 2.078  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.408      ;
; 2.081  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.405      ;
; 2.137  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.349      ;
; 2.208  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.278      ;
; 2.240  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 9.246      ;
; 2.361  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 9.117      ;
; 2.361  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 9.117      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.675 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.758     ; 1.164      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.298 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.425      ;
; -0.267 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.394      ;
; -0.256 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.372      ;
; -0.236 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.363      ;
; -0.234 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.350      ;
; -0.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.349      ;
; -0.229 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.356      ;
; -0.229 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.344      ;
; -0.228 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.343      ;
; -0.227 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.343      ;
; -0.221 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.348      ;
; -0.220 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.347      ;
; -0.205 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.321      ;
; -0.200 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.327      ;
; -0.200 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.316      ;
; -0.199 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.314      ;
; -0.198 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.325      ;
; -0.194 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.310      ;
; -0.192 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.308      ;
; -0.190 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.306      ;
; -0.188 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.315      ;
; -0.188 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.303      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.300      ;
; -0.181 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.296      ;
; -0.181 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.296      ;
; -0.181 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.297      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.295      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.304      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.305      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.304      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.305      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.303      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.303      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.289      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.289      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.298      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.297      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.296      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.295      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.294      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.293      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.292      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.292      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.287      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.285      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.285      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.285      ;
; -0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.283      ;
; -0.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.275      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.273      ;
; -0.132 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.259      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.247      ;
; -0.130 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.246      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.252      ;
; -0.099 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.226      ;
; -0.060 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.175      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.176      ;
; -0.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.168      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.153      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.151      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.153      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.142      ;
; -0.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.152      ;
; -0.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.153      ;
; -0.023 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.150      ;
; -0.014 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.141      ;
; -0.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.140      ;
; -0.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.137      ;
; -0.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.126      ;
; -0.008 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.135      ;
; -0.008 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.135      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.133      ;
; -0.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.132      ;
; -0.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.128      ;
; 0.004  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.112      ;
; 0.005  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.123      ;
; 0.011  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.116      ;
; 0.029  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.098      ;
; 0.030  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.098      ;
; 0.031  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.096      ;
; 0.120  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.007      ;
; 5.605  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.732     ; 6.271      ;
; 5.848  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.733     ; 6.027      ;
; 6.899  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.369     ; 5.340      ;
; 6.958  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 5.266      ;
; 7.291  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.933      ;
; 7.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.376     ; 4.819      ;
; 7.435  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.378     ; 4.795      ;
; 7.574  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.376     ; 4.658      ;
; 7.614  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.610      ;
; 7.648  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.378     ; 4.582      ;
; 7.692  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.532      ;
; 7.694  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.530      ;
; 7.825  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.399      ;
; 7.923  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.376     ; 4.309      ;
; 7.940  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.284      ;
; 8.038  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.186      ;
; 8.044  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.648      ; 6.019      ;
; 8.047  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.384     ; 4.177      ;
; 8.088  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.378     ; 4.142      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.214   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.279      ; 3.829      ;
; 195.222 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.193      ; 4.969      ;
; 195.350 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.303     ; 1.546      ;
; 196.733 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.196      ;
; 196.752 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.177      ;
; 196.862 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.067      ;
; 196.865 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.064      ;
; 196.867 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.062      ;
; 196.884 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.045      ;
; 196.886 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.043      ;
; 196.952 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.977      ;
; 196.989 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.940      ;
; 196.994 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.935      ;
; 196.997 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.932      ;
; 196.998 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.931      ;
; 196.999 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.930      ;
; 197.016 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.913      ;
; 197.017 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.912      ;
; 197.018 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.911      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.836      ;
; 197.084 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.845      ;
; 197.087 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.842      ;
; 197.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.811      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.808      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.808      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.803      ;
; 197.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.800      ;
; 197.130 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.799      ;
; 197.131 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.798      ;
; 197.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.792      ;
; 197.148 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.781      ;
; 197.149 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.780      ;
; 197.150 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.779      ;
; 197.216 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.713      ;
; 197.219 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.710      ;
; 197.219 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.710      ;
; 197.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.679      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.676      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.676      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.671      ;
; 197.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.671      ;
; 197.261 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.668      ;
; 197.262 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.667      ;
; 197.263 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.666      ;
; 197.264 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.665      ;
; 197.269 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.660      ;
; 197.280 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.649      ;
; 197.281 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.648      ;
; 197.282 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.647      ;
; 197.283 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.646      ;
; 197.348 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.581      ;
; 197.348 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.581      ;
; 197.351 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.578      ;
; 197.351 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.578      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.547      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.091     ; 2.525      ;
; 197.385 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.544      ;
; 197.385 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.544      ;
; 197.390 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.539      ;
; 197.390 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.539      ;
; 197.391 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.538      ;
; 197.393 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.536      ;
; 197.394 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.535      ;
; 197.395 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.534      ;
; 197.395 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.534      ;
; 197.396 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.533      ;
; 197.401 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.528      ;
; 197.412 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.517      ;
; 197.413 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.516      ;
; 197.414 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.515      ;
; 197.414 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.515      ;
; 197.415 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.479 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.450      ;
; 197.480 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.449      ;
; 197.480 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.449      ;
; 197.483 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.446      ;
; 197.483 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.446      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.022 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.191     ; 4.453      ;
; 1.022 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.191     ; 4.453      ;
; 1.129 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.191     ; 4.346      ;
; 1.129 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.191     ; 4.346      ;
; 1.151 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.360      ;
; 1.512 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.193     ; 3.961      ;
; 1.512 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.193     ; 3.961      ;
; 1.565 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.920      ;
; 1.630 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.193     ; 3.843      ;
; 1.630 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.193     ; 3.843      ;
; 1.649 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.952      ;
; 1.667 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.809      ;
; 1.671 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.930      ;
; 1.672 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.813      ;
; 1.675 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.801      ;
; 1.695 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.806      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.707 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.892      ;
; 1.714 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.887      ;
; 1.715 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.886      ;
; 1.722 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.879      ;
; 1.723 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.878      ;
; 1.760 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.727      ;
; 1.774 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.702      ;
; 1.782 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.190     ; 3.694      ;
; 1.802 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.702      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.845 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.755      ;
; 1.878 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.609      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.881 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.718      ;
; 1.933 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.554      ;
; 1.935 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.665      ;
; 1.936 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.664      ;
; 1.936 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.664      ;
; 1.955 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.545      ;
; 1.970 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.630      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.975 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.625      ;
; 1.986 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.192     ; 3.488      ;
; 2.033 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.169     ; 3.464      ;
; 2.066 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.533      ;
; 2.093 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.192     ; 3.381      ;
; 2.119 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.383      ;
; 2.158 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.352      ;
; 2.176 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.312      ;
; 2.176 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.312      ;
; 2.180 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 3.322      ;
; 2.208 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.280      ;
; 2.222 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.180     ; 3.264      ;
; 2.227 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.372      ;
; 2.229 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.370      ;
; 2.230 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.369      ;
; 2.230 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.369      ;
; 2.233 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.366      ;
; 2.243 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.357      ;
; 2.244 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.356      ;
; 2.260 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.227      ;
; 2.283 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.205      ;
; 2.283 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.205      ;
; 2.348 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.140      ;
; 2.362 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.188     ; 3.116      ;
; 2.440 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.073      ;
; 2.443 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.042      ;
; 2.443 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 3.042      ;
; 2.479 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.020      ;
; 2.497 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.116      ;
; 2.540 ; SDRAM_ADDR[2]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 2.949      ;
; 2.561 ; SDRAM_REQUEST                                                                             ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.073      ;
; 2.561 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 2.924      ;
; 2.561 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.181     ; 2.924      ;
; 2.613 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 2.890      ;
; 2.702 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.950      ;
; 2.731 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.757     ; 1.165      ;
; 2.769 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 2.720      ;
; 2.780 ; SDRAM_DI[10]                                                                              ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 2.834      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.773  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.573     ;
; 2.787  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.559     ;
; 2.865  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.481     ;
; 2.879  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.467     ;
; 2.905  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.441     ;
; 2.919  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.427     ;
; 2.922  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.424     ;
; 2.931  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.415     ;
; 3.014  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.332     ;
; 3.023  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.323     ;
; 3.054  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.292     ;
; 3.063  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.283     ;
; 3.113  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.233     ;
; 3.205  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.141     ;
; 3.245  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 14.101     ;
; 3.397  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.949     ;
; 3.411  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.935     ;
; 3.546  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.800     ;
; 3.555  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.791     ;
; 3.592  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 13.753     ;
; 3.684  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 13.661     ;
; 3.724  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 13.621     ;
; 3.737  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.609     ;
; 3.894  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 13.467     ;
; 3.908  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.438     ;
; 3.922  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.424     ;
; 3.927  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.419     ;
; 3.941  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.405     ;
; 3.986  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 13.375     ;
; 4.026  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 13.335     ;
; 4.057  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.289     ;
; 4.066  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.280     ;
; 4.076  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.270     ;
; 4.085  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.261     ;
; 4.216  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 13.129     ;
; 4.248  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.098     ;
; 4.267  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 13.079     ;
; 4.475  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 12.871     ;
; 4.489  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 12.857     ;
; 4.518  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 12.843     ;
; 4.624  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 12.722     ;
; 4.633  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 12.713     ;
; 4.727  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 12.618     ;
; 4.746  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 12.599     ;
; 4.815  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 12.531     ;
; 5.029  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 12.332     ;
; 5.048  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 12.313     ;
; 5.294  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 12.051     ;
; 5.439  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.757     ; 1.394      ;
; 5.596  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 11.765     ;
; 6.267  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 11.079     ;
; 6.281  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 11.065     ;
; 6.416  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 10.930     ;
; 6.425  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 10.921     ;
; 6.607  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 10.739     ;
; 7.086  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 10.259     ;
; 7.388  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.168     ; 9.973      ;
; 7.608  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.853      ;
; 7.669  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.792      ;
; 7.700  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.761      ;
; 7.740  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.721      ;
; 7.761  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.700      ;
; 7.779  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.682      ;
; 7.801  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.660      ;
; 7.871  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.590      ;
; 7.911  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.550      ;
; 7.933  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 9.527      ;
; 8.025  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 9.435      ;
; 8.065  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 9.395      ;
; 8.232  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.229      ;
; 8.293  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.168      ;
; 8.403  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 9.058      ;
; 8.557  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.903      ;
; 8.565  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.895      ;
; 8.657  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.803      ;
; 8.697  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.763      ;
; 8.743  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.718      ;
; 8.762  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.699      ;
; 8.804  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.657      ;
; 8.823  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.638      ;
; 8.914  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.547      ;
; 8.933  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.528      ;
; 9.068  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.392      ;
; 9.087  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.373      ;
; 9.189  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 8.271      ;
; 9.310  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.151      ;
; 9.371  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 8.090      ;
; 9.481  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 7.980      ;
; 9.635  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 7.825      ;
; 9.700  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 7.760      ;
; 9.719  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 7.741      ;
; 10.267 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 7.193      ;
; 11.102 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 6.359      ;
; 11.163 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 6.298      ;
; 11.273 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.068     ; 6.188      ;
; 11.427 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 6.033      ;
; 11.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.905      ;
; 11.473 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.886      ;
; 11.547 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.173     ; 5.809      ;
; 11.566 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.173     ; 5.790      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                    ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.823 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.897      ;
; -1.739 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.981      ;
; -1.738 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.982      ;
; -1.737 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.983      ;
; -1.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.998      ;
; -1.722 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 0.998      ;
; -1.702 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.018      ;
; -1.700 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.020      ;
; -1.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.020      ;
; -1.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.032      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.037      ;
; -1.681 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.027      ;
; -1.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.043      ;
; -1.675 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.045      ;
; -1.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.047      ;
; -1.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.047      ;
; -1.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.048      ;
; -1.670 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.050      ;
; -1.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.058      ;
; -1.660 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.060      ;
; -1.654 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.053      ;
; -1.650 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.070      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.076      ;
; -1.642 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.078      ;
; -1.641 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.066      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.082      ;
; -1.632 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.076      ;
; -1.631 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.076      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.091      ;
; -1.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.092      ;
; -1.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.080      ;
; -1.627 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.080      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.094      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.082      ;
; -1.620 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.100      ;
; -1.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.101      ;
; -1.615 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.092      ;
; -1.615 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.093      ;
; -1.614 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.094      ;
; -1.613 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.095      ;
; -1.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.096      ;
; -1.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.110      ;
; -1.610 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.111      ;
; -1.609 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.112      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.114      ;
; -1.604 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.117      ;
; -1.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.118      ;
; -1.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.120      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.121      ;
; -1.598 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.122      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.110      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.123      ;
; -1.596 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.124      ;
; -1.591 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.129      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.133      ;
; -1.586 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.121      ;
; -1.586 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.121      ;
; -1.585 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.135      ;
; -1.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.123      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.141      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.140      ;
; -1.578 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.129      ;
; -1.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.135      ;
; -1.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.147      ;
; -1.559 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.161      ;
; -1.556 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.164      ;
; -1.551 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.156      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.425      ; 1.213      ;
; -1.501 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.220      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.219      ;
; -1.486 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.235      ;
; -1.486 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.222      ;
; -1.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.237      ;
; -1.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.227      ;
; -1.463 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.258      ;
; -1.462 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.258      ;
; -1.460 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.247      ;
; -1.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.253      ;
; -1.452 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.413      ; 1.255      ;
; -1.446 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.274      ;
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.337      ;
; 0.393  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.427      ; 1.042      ;
; 0.408  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.427      ; 1.057      ;
; 0.408  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.427      ; 1.057      ;
; 0.411  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 1.058      ;
; 0.411  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.427      ; 1.060      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                    ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                        ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.824 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.099      ; 3.627      ;
; 0.439  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.695      ;
; 0.441  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.697      ;
; 0.453  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.708      ;
; 0.543  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.193     ; 1.483      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.911      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.911      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.911      ;
; 0.657  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.912      ;
; 0.658  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.913      ;
; 0.659  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.914      ;
; 0.659  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.914      ;
; 0.669  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.924      ;
; 0.673  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.928      ;
; 0.681  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.936      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.225      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.225      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.973  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.228      ;
; 0.974  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.229      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.235      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.235      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.236      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.236      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.237      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.237      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.238      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.238      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.240      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.240      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.240      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.242      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.242      ;
; 0.988  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.243      ;
; 0.990  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.245      ;
; 0.991  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.246      ;
; 0.991  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.246      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.255      ;
; 1.005  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.260      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.346      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.346      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.094  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.349      ;
; 1.095  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.350      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.351      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.351      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.099  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.354      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.361      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.361      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.363      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.363      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.364      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.366      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.366      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.366      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.995      ;
; 0.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.996      ;
; 0.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.998      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.002      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.457      ; 1.031      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.007      ;
; 0.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.010      ;
; 0.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.014      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.016      ;
; 0.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.022      ;
; 0.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.024      ;
; 0.369 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.025      ;
; 0.370 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.026      ;
; 0.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.025      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.029      ;
; 0.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.029      ;
; 0.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.032      ;
; 0.377 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.033      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.044      ;
; 0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.046      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.433      ; 1.051      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.054      ;
; 0.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 0.669      ;
; 0.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.050      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.056      ;
; 0.406 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.053      ;
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.064      ;
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.062      ;
; 0.407 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.061      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.060      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.063      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.064      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                  ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                           ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                              ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                             ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.412 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|sdram_rdy                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_request_reg                                     ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_wr_act                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.674      ;
; 0.461 ; seq_reg[11]                                           ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.718      ;
; 0.471 ; seq_reg[5]                                            ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.727      ;
; 0.471 ; seq_reg[8]                                            ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.727      ;
; 0.506 ; seq_reg[7]                                            ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.762      ;
; 0.568 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.825      ;
; 0.601 ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.858      ;
; 0.601 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.858      ;
; 0.602 ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.859      ;
; 0.603 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.859      ;
; 0.628 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.884      ;
; 0.634 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.890      ;
; 0.645 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.901      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.662 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.918      ;
; 0.666 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.676 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.933      ;
; 0.677 ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.933      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.944      ;
; 0.688 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.945      ;
; 0.696 ; seq_reg[10]                                           ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.704 ; sdram_request_complete_reg                            ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.960      ;
; 0.793 ; seq_reg[6]                                            ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.048      ;
; 0.809 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.065      ;
; 0.816 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.073      ;
; 0.817 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.074      ;
; 0.871 ; seq_reg[4]                                            ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.128      ;
; 0.886 ; sdram_ctrl:sdram_controller|r_rd_reg                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.142      ;
; 0.888 ; sdram_ctrl:sdram_controller|r_wr_act                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.144      ;
; 0.889 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.146      ;
; 0.894 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.150      ;
; 0.918 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.175      ;
; 0.945 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.202      ;
; 0.946 ; seq_reg[2]                                            ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.202      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.219      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.219      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.219      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.975 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.231      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.980 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.236      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.986 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.243      ;
; 1.012 ; seq_reg[9]                                            ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.270      ;
; 1.019 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.025 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.054 ; seq_reg[4]                                            ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.310      ;
; 1.059 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.317      ;
; 1.066 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.323      ;
; 1.080 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.337      ;
; 1.084 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.340      ;
; 1.084 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.340      ;
; 1.084 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.340      ;
; 1.089 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.345      ;
; 1.089 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.345      ;
; 1.089 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.345      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.357      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.361      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.105 ; sdram_ctrl:sdram_controller|r_wr_reg                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 1.347      ;
; 1.106 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.362      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.122 ; seq_reg[0]                                            ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.378      ;
; 1.125 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.382      ;
; 1.129 ; seq_reg[9]                                            ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.387      ;
; 1.150 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.406      ;
; 1.151 ; sdram_request_reg                                     ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.419      ;
; 1.156 ; seq_reg[10]                                           ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.416      ;
; 1.166 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 1.419      ;
; 1.202 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.460      ;
; 1.205 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.461      ;
; 1.210 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.466      ;
; 1.210 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.466      ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                     ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.414 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.669      ;
; 0.653 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.909      ;
; 0.882 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.137      ;
; 0.923 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.178      ;
; 0.987 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.242      ;
; 0.997 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 1.253      ;
; 1.003 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.258      ;
; 1.017 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.272      ;
; 1.031 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.286      ;
; 1.032 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.287      ;
; 1.202 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.457      ;
; 1.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 1.729      ;
; 1.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 1.730      ;
; 1.338 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.593      ;
; 1.395 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.157      ; 1.848      ;
; 1.396 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.157      ; 1.849      ;
; 1.414 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 1.670      ;
; 1.430 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.157      ; 1.883      ;
; 1.511 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 1.974      ;
; 1.527 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 1.991      ;
; 1.527 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 1.991      ;
; 1.527 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 1.991      ;
; 1.617 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.069      ;
; 1.828 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.084      ;
; 1.844 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.100      ;
; 1.871 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.127      ;
; 1.887 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.143      ;
; 1.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.427      ;
; 1.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.452      ;
; 2.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.538      ;
; 2.089 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.554      ;
; 2.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.569      ;
; 2.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.602      ;
; 2.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.606      ;
; 2.150 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.602      ;
; 2.150 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.602      ;
; 2.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.636      ;
; 2.197 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.662      ;
; 2.221 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.477      ;
; 2.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.683      ;
; 2.237 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.493      ;
; 2.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 2.731      ;
; 2.268 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.723      ;
; 2.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 2.736      ;
; 2.280 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 2.747      ;
; 2.294 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.749      ;
; 2.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.800      ;
; 2.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.804      ;
; 2.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.821      ;
; 2.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.847      ;
; 2.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.849      ;
; 2.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.881      ;
; 2.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.875      ;
; 2.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.892      ;
; 2.438 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.903      ;
; 2.446 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.911      ;
; 2.466 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.931      ;
; 2.471 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 2.936      ;
; 2.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.964      ;
; 2.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.975      ;
; 2.537 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.992      ;
; 2.538 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.003      ;
; 2.538 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.993      ;
; 2.543 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 2.998      ;
; 2.546 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.001      ;
; 2.553 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.008      ;
; 2.553 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.018      ;
; 2.564 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.029      ;
; 2.576 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.043      ;
; 2.592 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.057      ;
; 2.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.062      ;
; 2.609 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.064      ;
; 2.630 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.097      ;
; 2.655 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.110      ;
; 2.660 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.115      ;
; 2.664 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.119      ;
; 2.669 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.124      ;
; 2.679 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.144      ;
; 2.701 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.156      ;
; 2.702 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.169      ;
; 2.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.172      ;
; 2.718 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.183      ;
; 2.726 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.181      ;
; 2.726 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 2.982      ;
; 2.756 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.223      ;
; 2.781 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.236      ;
; 2.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.241      ;
; 2.790 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.245      ;
; 2.796 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.173      ; 3.265      ;
; 2.823 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.173      ; 3.292      ;
; 2.828 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.295      ;
; 2.831 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.173      ; 3.300      ;
; 2.843 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.308      ;
; 2.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.302      ;
; 2.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.173      ; 3.321      ;
; 2.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.307      ;
; 2.863 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.318      ;
; 2.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.159      ; 3.323      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.635 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.504     ; 1.023      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.232      ; 3.505      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
; -2.208 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.390      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.325 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.281      ; 4.370      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.364      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.625 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.857      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.844      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.844      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.844      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.844      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.844      ;
; 7.656 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.186     ; 3.814      ;
; 7.698 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.784      ;
; 7.698 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.784      ;
; 8.064 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 3.407      ;
; 8.070 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 3.410      ;
; 8.070 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 3.410      ;
; 8.070 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 3.410      ;
; 8.070 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[30]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[31]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[18]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[18]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[24]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[24]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[5]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 3.406      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.405      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.410      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.394      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.394      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.393      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.393      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.394      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.393      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.394      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.393      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.191     ; 3.393      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 3.394      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
; 8.072 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.404      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                           ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.963 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.284     ; 3.286      ;
; 8.040 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 3.307      ;
; 8.040 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 3.307      ;
; 8.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.279      ;
; 8.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.290      ;
; 8.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.278      ;
; 8.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.277      ;
; 8.057 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.277      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.285      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.285      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.207     ; 3.274      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.273      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.285      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.285      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.273      ;
; 8.059 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 3.285      ;
; 8.073 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.332     ; 3.127      ;
; 8.073 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.332     ; 3.127      ;
; 8.073 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.332     ; 3.127      ;
; 8.073 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.335     ; 3.124      ;
; 8.073 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.335     ; 3.124      ;
; 8.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.346     ; 3.112      ;
; 8.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.346     ; 3.112      ;
; 8.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.346     ; 3.112      ;
; 8.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.344     ; 3.113      ;
; 8.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.343     ; 3.114      ;
; 8.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.344     ; 3.113      ;
; 8.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.344     ; 3.113      ;
; 8.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.336     ; 3.120      ;
; 8.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.350     ; 3.105      ;
; 8.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.343     ; 3.112      ;
; 8.081 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.240      ;
; 8.081 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.240      ;
; 8.081 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.221     ; 3.240      ;
; 8.081 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 3.237      ;
; 8.081 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 3.237      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.235     ; 3.225      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.235     ; 3.225      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.235     ; 3.225      ;
; 8.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.227      ;
; 8.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.233     ; 3.226      ;
; 8.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.233     ; 3.226      ;
; 8.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.233     ; 3.226      ;
; 8.084 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 3.233      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.225      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.218      ;
; 8.179 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.303      ;
; 8.179 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.303      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.041      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.041      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.041      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.030      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.041      ;
; 8.305 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 3.041      ;
; 8.563 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.905      ;
; 8.563 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.905      ;
; 8.563 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.905      ;
; 8.563 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.905      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.916      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.916      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.916      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.916      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.917      ;
; 8.564 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 2.921      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.892      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.892      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.892      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.892      ;
; 8.567 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.892      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 4.381      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 4.381      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 4.381      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.961 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.382      ;
; 12.962 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.381      ;
; 12.962 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.381      ;
; 12.962 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 4.381      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.101      ; 4.119      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
; -0.332 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.095      ; 4.115      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.337 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.164      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
; 0.566 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 3.288      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.480 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.352      ; 2.018      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 1.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.333      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.159      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.159      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.159      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.159      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.162      ; 3.159      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.167      ; 3.164      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
; 2.700 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.165      ; 3.162      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.256 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.256 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.720      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.719      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.719      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.719      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.719      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.701      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.257 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 2.724      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.699      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 2.697      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.700      ;
; 2.258 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.510 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.857      ;
; 2.510 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.857      ;
; 2.510 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.857      ;
; 2.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.858      ;
; 2.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.117      ; 2.847      ;
; 2.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.858      ;
; 2.630 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.094      ;
; 2.630 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.094      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.131      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.131      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 4.131      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 4.132      ;
; 3.681 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 4.131      ;
; 3.681 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 4.131      ;
; 3.681 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 4.131      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[6]                   ;
; 5.657 ; 5.815        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.720 ; 5.850        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.785 ; 5.896        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.850 ; 5.850        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.896 ; 5.896        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.657  ; 8.787        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.722  ; 8.833        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.374  ; 10.404       ; 1.030          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                             ;
; 9.397  ; 10.427       ; 1.030          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                             ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                                        ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                    ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                            ;
; 10.135 ; 10.355       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                            ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En                        ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En                         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit                      ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[2]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC                         ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]                              ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC                          ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready                                ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]                                ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC                            ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[0]                             ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready                                  ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy                 ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt               ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[1]                             ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[2]                             ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                              ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                              ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                              ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                              ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[1]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[2]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[1]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[2]                           ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010                                       ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011                                       ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                                      ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                                    ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                                    ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn                                                    ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                                   ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                 ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                                    ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                          ;
; 10.141 ; 10.361       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.259 ; 17.610       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.261 ; 17.612       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.337 ; 17.557       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1]         ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq             ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq               ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq                 ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq           ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq               ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[4]                                                                                                 ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[5]                                                                                                 ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[6]                                                                                                 ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[7]                                                                                                 ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                                                                                         ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                                                                                         ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                                                                                         ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                                                                                         ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[3]                                                                                          ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[1]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[2]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[3]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[4]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[5]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[6]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_raw_reg[7]                                                                                                ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[2]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[3]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[4]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[5]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[6]                                                                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colbk_snap_reg[7]                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.595 ; 17.595       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.604 ; 17.604       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.638 ; 17.638       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.530  ; 99.833       ; 10.303         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.864  ; 100.167      ; 10.303         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.677  ; 99.865       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.679  ; 99.867       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.679  ; 99.867       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.679  ; 99.867       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.679  ; 99.867       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.818  ; 99.818       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.830  ; 99.830       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.832  ; 99.832       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.832  ; 99.832       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.832  ; 99.832       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.832  ; 99.832       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.850  ; 99.850       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.852  ; 99.852       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.912  ; 100.132      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.912  ; 100.132      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.912  ; 100.132      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.912  ; 100.132      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.913  ; 100.133      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.770 ; 2.949 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.755 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.763 ; 2.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.755 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.703 ; 2.881 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.763 ; 2.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.770 ; 2.949 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.292 ; 3.505 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.779 ; 0.958 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.782 ; 0.961 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.880 ; -2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.881 ; -2.060 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.880 ; -2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.896 ; -2.075 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.340 ; -2.542 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.161 ; -0.340 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.179 ; -0.358 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.182 ; -0.361 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.164 ; -0.343 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.361  ; 2.340  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 6.385  ; 6.825  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.750  ; 4.724  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.656  ; 3.596  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.675  ; 3.622  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.834  ; 3.905  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.185  ; 7.486  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.788  ; 4.605  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.185  ; 7.486  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.603  ; 4.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.085  ; 4.905  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.628  ; 7.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 5.060  ; 4.871  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.156  ; 4.933  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 5.168  ; 4.946  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.628  ; 7.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.826 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.176 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 6.119  ; 6.475  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.724  ; 3.597  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.119  ; 6.475  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.518  ; 3.407  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.195  ; 4.097  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 6.531  ; 6.860  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.991  ; 3.858  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.068  ; 3.969  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.087  ; 3.981  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.531  ; 6.860  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.261  ; 4.249  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.078  ; 4.057  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.477  ; 1.403  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.277  ; 2.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.277  ; 2.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.280  ; 2.072  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.280  ; 2.072  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.268  ; 2.060  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.268  ; 2.060  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.266  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.477  ; 1.403  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.882  ; 5.134  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.277  ; 2.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.489  ; 1.415  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.894  ; 5.146  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.489  ; 1.415  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.491  ; 1.417  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.636  ; 1.616  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.647  ; 2.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.647  ; 2.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.647  ; 2.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.250  ; 4.675  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.242  ; 4.667  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.636  ; 1.616  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.464  ; 2.317  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.636  ; 2.498  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.235  ; 4.660  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.633  ; 2.495  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.633  ; 2.495  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.633  ; 2.495  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.241  ; 4.666  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.635  ; 2.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.635  ; 2.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.268  ; 2.060  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.896  ; 5.148  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 5.514  ; 5.952  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 3.840  ; 3.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.790  ; 2.729  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.807  ; 2.754  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.957  ; 3.028  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.555  ; 3.420  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.734  ; 3.578  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.139  ; 6.467  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.555  ; 3.420  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.818  ; 3.670  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.956  ; 3.793  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.993  ; 3.831  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.956  ; 3.793  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.966  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.563  ; 6.862  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.041 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.392 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.657  ; 2.546  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.856  ; 2.730  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.258  ; 5.616  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.657  ; 2.546  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.233  ; 3.139  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.112  ; 2.979  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.112  ; 2.979  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.183  ; 3.085  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.201  ; 3.097  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.655  ; 5.985  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.793  ; 3.782  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.596  ; 3.576  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.206  ; 6.631  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.610  ; 3.590  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.639 ; 3.563 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.639 ; 3.563 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.639 ; 3.563 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.639 ; 3.563 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.087 ; 6.448 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.419 ; 6.780 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.162 ; 4.076 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.138 ; 4.052 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.549 ; 4.401 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.705 ; 4.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.817 ; 7.178 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.043 ; 3.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.043 ; 3.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.043 ; 3.967 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.447 ; 6.808 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.017 ; 3.941 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.017 ; 3.941 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.716 ; 3.568 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 6.115 ; 6.039 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.484 ; 5.398 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.863 ; 9.224 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 5.070 ; 4.984 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.789 ; 2.713 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.789 ; 2.713 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.789 ; 2.713 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.789 ; 2.713 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.237 ; 5.598 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.555 ; 5.916 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.284 ; 3.198 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.261 ; 3.175 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.620 ; 3.472 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.813 ; 3.737 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.937 ; 6.298 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.177 ; 3.101 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.177 ; 3.101 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.177 ; 3.101 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.582 ; 5.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.152 ; 3.076 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.152 ; 3.076 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.821 ; 2.673 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.492 ; 5.416 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.880 ; 4.794 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.228 ; 8.589 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.482 ; 4.396 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.579     ; 3.655     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.579     ; 3.655     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.579     ; 3.655     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.579     ; 3.655     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.465     ; 6.104     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.792     ; 6.431     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.083     ; 4.169     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.046     ; 4.132     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.363     ; 4.511     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.640     ; 4.716     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 7.197     ; 6.836     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.990     ; 4.066     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.990     ; 4.066     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.990     ; 4.066     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.827     ; 6.466     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.960     ; 4.036     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.960     ; 4.036     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.594     ; 3.742     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 6.032     ; 6.108     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.397     ; 5.483     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 9.209     ; 8.848     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.990     ; 5.076     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.728     ; 2.804     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.728     ; 2.804     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.728     ; 2.804     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.728     ; 2.804     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.614     ; 5.253     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.928     ; 5.567     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.205     ; 3.291     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.169     ; 3.255     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.436     ; 3.584     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.747     ; 3.823     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.316     ; 5.955     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.123     ; 3.199     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.123     ; 3.199     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.123     ; 3.199     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.961     ; 5.600     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.094     ; 3.170     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.094     ; 3.170     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.697     ; 2.845     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.410     ; 5.486     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.793     ; 4.879     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.574     ; 8.213     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.402     ; 4.488     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 39.32 MHz  ; 39.32 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 111.71 MHz ; 111.71 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 112.96 MHz ; 100.0 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; limit due to minimum period restriction (tmin) ;
; 156.35 MHz ; 156.35 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 213.81 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.269 ; -243.298      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.389 ; -1.389        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.294 ; -11.110       ;
; FPGA_CLK                                                                            ; 0.075  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.477  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.247  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.607 ; -113.520      ;
; FPGA_CLK                                                                            ; -0.675 ; -0.675        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.346  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.362  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.362  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.380 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.167 ; -19.503       ;
; FPGA_CLK                                                                            ; -0.334 ; -8.670        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.016  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.340  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.376 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.253 ; -6.564        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.302  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.343  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.014  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.277  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.596  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.733  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.533  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.370  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.282 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.643 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.269 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 1.101      ;
; -3.196 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 1.028      ;
; -3.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.909      ;
; -3.064 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.896      ;
; -3.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.883      ;
; -3.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.880      ;
; -3.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.877      ;
; -3.023 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.149     ; 0.844      ;
; -3.017 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.848      ;
; -3.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.840      ;
; -2.901 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.158     ; 0.713      ;
; -2.899 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.158     ; 0.711      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.149     ; 0.713      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.149     ; 0.710      ;
; -2.880 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.140     ; 0.710      ;
; -2.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.139     ; 0.710      ;
; -2.847 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 1.040      ;
; -2.821 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 1.028      ;
; -2.815 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.768     ; 1.017      ;
; -2.741 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.901      ;
; -2.721 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.881      ;
; -2.717 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.881      ;
; -2.716 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.880      ;
; -2.703 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.910      ;
; -2.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.908      ;
; -2.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.894      ;
; -2.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.908      ;
; -2.699 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.906      ;
; -2.699 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.906      ;
; -2.695 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.902      ;
; -2.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.881      ;
; -2.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.884      ;
; -2.676 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.883      ;
; -2.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.881      ;
; -2.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.777     ; 0.867      ;
; -2.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.880      ;
; -2.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.766     ; 0.870      ;
; -2.665 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.871      ;
; -2.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.867      ;
; -2.657 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.860      ;
; -2.654 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.857      ;
; -2.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.841      ;
; -2.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.829      ;
; -2.591 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.751      ;
; -2.589 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.753      ;
; -2.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.751      ;
; -2.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.751      ;
; -2.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.741      ;
; -2.573 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.733      ;
; -2.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.732      ;
; -2.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.732      ;
; -2.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.733      ;
; -2.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.734      ;
; -2.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.732      ;
; -2.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.732      ;
; -2.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.806     ; 0.731      ;
; -2.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.731      ;
; -2.564 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.733      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.800     ; 0.733      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.732      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.731      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.800     ; 0.732      ;
; -2.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.800     ; 0.731      ;
; -2.557 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.795     ; 0.732      ;
; -2.556 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.795     ; 0.731      ;
; -2.555 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.795     ; 0.730      ;
; -2.551 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.754      ;
; -2.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.753      ;
; -2.548 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.751      ;
; -2.546 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.753      ;
; -2.543 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.763     ; 0.750      ;
; -2.542 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.711      ;
; -2.540 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.709      ;
; -2.540 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.800     ; 0.710      ;
; -2.536 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.795     ; 0.711      ;
; -2.535 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.795     ; 0.710      ;
; -2.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.733      ;
; -2.526 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.787     ; 0.709      ;
; -2.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.731      ;
; -2.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.731      ;
; -2.521 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.753      ;
; -2.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.752      ;
; -2.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.750      ;
; -2.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.750      ;
; -2.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 0.710      ;
; -2.515 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 0.709      ;
; -2.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.712      ;
; -2.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.711      ;
; -2.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.764     ; 0.711      ;
; -2.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.732      ;
; -2.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.738     ; 0.731      ;
; 2.685  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.819      ;
; 2.840  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.664      ;
; 2.848  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.656      ;
; 2.849  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.655      ;
; 2.900  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.604      ;
; 2.975  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.529      ;
; 2.980  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.524      ;
; 3.100  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.412      ;
; 3.100  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.412      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.389 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.570     ; 1.082      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.294 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.287      ;
; -0.258 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.251      ;
; -0.244 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.228      ;
; -0.243 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.227      ;
; -0.243 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.227      ;
; -0.237 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.230      ;
; -0.236 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.230      ;
; -0.227 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.220      ;
; -0.224 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.208      ;
; -0.223 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.207      ;
; -0.220 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.213      ;
; -0.214 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.208      ;
; -0.214 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.207      ;
; -0.213 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.197      ;
; -0.212 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.196      ;
; -0.211 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.195      ;
; -0.211 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.195      ;
; -0.203 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.196      ;
; -0.194 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.188      ;
; -0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.170      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.167      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.168      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.087      ; 1.164      ;
; -0.176 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.159      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.159      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.166      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.156      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.156      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.155      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.160      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.150      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.150      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.158      ;
; -0.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.157      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.154      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.154      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.152      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.152      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.150      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.151      ;
; -0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.149      ;
; -0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.147      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.147      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.146      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.131      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.140      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.139      ;
; -0.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.136      ;
; -0.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.133      ;
; -0.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.123      ;
; -0.123 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.116      ;
; -0.089 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.073      ;
; -0.080 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.064      ;
; -0.069 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.062      ;
; -0.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.050      ;
; -0.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.053      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.036      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.034      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.042      ;
; -0.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.035      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.034      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.034      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.031      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.031      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.020      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.030      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.028      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.028      ;
; -0.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.025      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.024      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.023      ;
; -0.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.004      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 1.000      ;
; 0.008  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 0.985      ;
; 0.008  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 0.985      ;
; 0.009  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 0.984      ;
; 0.073  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.095      ; 0.920      ;
; 5.990  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.675     ; 5.778      ;
; 6.239  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.676     ; 5.528      ;
; 7.090  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.353     ; 5.000      ;
; 7.281  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.798      ;
; 7.576  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.503      ;
; 7.711  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 4.375      ;
; 7.732  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.359     ; 4.352      ;
; 7.828  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 4.258      ;
; 7.857  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.222      ;
; 7.884  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.195      ;
; 7.902  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.177      ;
; 7.917  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.359     ; 4.167      ;
; 8.064  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 4.015      ;
; 8.164  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 3.922      ;
; 8.172  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 3.907      ;
; 8.203  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 3.876      ;
; 8.204  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.364     ; 3.875      ;
; 8.238  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.231      ; 5.409      ;
; 8.291  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.231      ; 5.356      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.075   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.879      ; 3.569      ;
; 195.323 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.174      ; 4.850      ;
; 195.512 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.272     ; 1.442      ;
; 197.094 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.840      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.811      ;
; 197.198 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.736      ;
; 197.210 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.724      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.722      ;
; 197.239 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.695      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.693      ;
; 197.285 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.649      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.303 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.617      ;
; 197.310 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.624      ;
; 197.314 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.620      ;
; 197.326 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.608      ;
; 197.327 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.607      ;
; 197.328 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.606      ;
; 197.355 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.579      ;
; 197.356 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.578      ;
; 197.357 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.577      ;
; 197.401 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.533      ;
; 197.405 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.529      ;
; 197.426 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.508      ;
; 197.426 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.508      ;
; 197.430 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.504      ;
; 197.432 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.502      ;
; 197.442 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.492      ;
; 197.443 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.491      ;
; 197.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.490      ;
; 197.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.473      ;
; 197.471 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.463      ;
; 197.472 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.462      ;
; 197.473 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.461      ;
; 197.517 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.417      ;
; 197.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.413      ;
; 197.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.413      ;
; 197.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.392      ;
; 197.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.392      ;
; 197.546 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.388      ;
; 197.547 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.387      ;
; 197.548 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.386      ;
; 197.558 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.376      ;
; 197.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.375      ;
; 197.560 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.374      ;
; 197.561 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.373      ;
; 197.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.357      ;
; 197.587 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.347      ;
; 197.588 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.346      ;
; 197.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.345      ;
; 197.590 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.344      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.597 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.081     ; 2.321      ;
; 197.633 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.301      ;
; 197.634 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.300      ;
; 197.637 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.297      ;
; 197.637 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.297      ;
; 197.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.276      ;
; 197.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.276      ;
; 197.662 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.272      ;
; 197.663 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.271      ;
; 197.663 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.271      ;
; 197.664 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.270      ;
; 197.674 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.260      ;
; 197.675 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.259      ;
; 197.676 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.258      ;
; 197.676 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.258      ;
; 197.677 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.257      ;
; 197.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.241      ;
; 197.703 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.231      ;
; 197.704 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.230      ;
; 197.705 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.229      ;
; 197.705 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.229      ;
; 197.706 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.228      ;
; 197.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.186      ;
; 197.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.185      ;
; 197.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.184      ;
; 197.753 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.181      ;
; 197.753 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.065     ; 2.181      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.477 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 4.034      ;
; 1.477 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 4.034      ;
; 1.479 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.062      ;
; 1.586 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.925      ;
; 1.586 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.925      ;
; 1.835 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.675      ;
; 1.835 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.675      ;
; 1.899 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.621      ;
; 1.944 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.566      ;
; 1.944 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.566      ;
; 1.998 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.522      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.001 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.631      ;
; 2.040 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.594      ;
; 2.052 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.582      ;
; 2.064 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.449      ;
; 2.074 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 3.460      ;
; 2.075 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.437      ;
; 2.077 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.557      ;
; 2.078 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.556      ;
; 2.084 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.550      ;
; 2.085 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.549      ;
; 2.090 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.433      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.142 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.491      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.459      ;
; 2.173 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.340      ;
; 2.184 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.328      ;
; 2.192 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.344      ;
; 2.199 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.324      ;
; 2.247 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.273      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.258 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.375      ;
; 2.268 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.264      ;
; 2.281 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.230      ;
; 2.295 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 3.233      ;
; 2.301 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.332      ;
; 2.302 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.331      ;
; 2.302 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.331      ;
; 2.337 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.296      ;
; 2.390 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.121      ;
; 2.427 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.106      ;
; 2.443 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.190      ;
; 2.483 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.041      ;
; 2.483 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 3.041      ;
; 2.485 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.056      ;
; 2.511 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.009      ;
; 2.528 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 2.993      ;
; 2.539 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.995      ;
; 2.556 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.077      ;
; 2.557 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.076      ;
; 2.582 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.051      ;
; 2.584 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.049      ;
; 2.585 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.048      ;
; 2.586 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.047      ;
; 2.589 ; SDRAM_WRITE_ENABLE                                                                        ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.149     ; 3.044      ;
; 2.592 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 2.932      ;
; 2.592 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.146     ; 2.932      ;
; 2.600 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 2.922      ;
; 2.622 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.898      ;
; 2.708 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 2.805      ;
; 2.716 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.804      ;
; 2.716 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.804      ;
; 2.768 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.777      ;
; 2.801 ; SDRAM_REQUEST                                                                             ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 2.860      ;
; 2.807 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.837      ;
; 2.810 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.721      ;
; 2.825 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.695      ;
; 2.825 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.695      ;
; 2.850 ; SDRAM_ADDR[2]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 2.672      ;
; 2.877 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.657      ;
; 2.965 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.103     ; 2.714      ;
; 3.017 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.569     ; 1.083      ;
; 3.021 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.499      ;
; 3.021 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 2.499      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 4.247  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 13.124     ;
; 4.260  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 13.111     ;
; 4.301  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 13.070     ;
; 4.314  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 13.057     ;
; 4.363  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 13.008     ;
; 4.376  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.995     ;
; 4.389  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.982     ;
; 4.421  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.950     ;
; 4.443  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.928     ;
; 4.475  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.896     ;
; 4.505  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.866     ;
; 4.537  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.834     ;
; 4.573  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.798     ;
; 4.627  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.744     ;
; 4.684  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.687     ;
; 4.689  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.682     ;
; 4.697  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.674     ;
; 4.826  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.545     ;
; 4.858  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.513     ;
; 5.010  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.361     ;
; 5.033  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 12.337     ;
; 5.087  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 12.283     ;
; 5.149  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 12.221     ;
; 5.204  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.167     ;
; 5.217  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.154     ;
; 5.253  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 12.131     ;
; 5.271  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.100     ;
; 5.284  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.087     ;
; 5.307  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 12.077     ;
; 5.346  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 12.025     ;
; 5.369  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 12.015     ;
; 5.378  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.993     ;
; 5.413  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.958     ;
; 5.445  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.926     ;
; 5.470  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 11.900     ;
; 5.530  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.841     ;
; 5.597  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.774     ;
; 5.690  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 11.694     ;
; 5.697  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.674     ;
; 5.710  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.661     ;
; 5.746  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.569     ; 1.291      ;
; 5.839  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.532     ;
; 5.871  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.500     ;
; 5.990  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 11.380     ;
; 6.023  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 11.348     ;
; 6.057  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 11.313     ;
; 6.210  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 11.174     ;
; 6.277  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 11.107     ;
; 6.483  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 10.887     ;
; 6.703  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 10.681     ;
; 7.356  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 10.015     ;
; 7.369  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 10.002     ;
; 7.498  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 9.873      ;
; 7.530  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 9.841      ;
; 7.682  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 9.689      ;
; 8.142  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.160     ; 9.228      ;
; 8.362  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.146     ; 9.022      ;
; 8.669  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.799      ;
; 8.677  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.791      ;
; 8.723  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.745      ;
; 8.731  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.737      ;
; 8.765  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.703      ;
; 8.785  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.683      ;
; 8.793  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.675      ;
; 8.819  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.649      ;
; 8.881  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.587      ;
; 8.965  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 8.502      ;
; 9.019  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 8.448      ;
; 9.081  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 8.386      ;
; 9.106  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.362      ;
; 9.116  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.352      ;
; 9.202  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 8.266      ;
; 9.404  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 8.063      ;
; 9.509  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.958      ;
; 9.563  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.904      ;
; 9.625  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.842      ;
; 9.626  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.842      ;
; 9.636  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.832      ;
; 9.693  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.775      ;
; 9.701  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.767      ;
; 9.722  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.746      ;
; 9.789  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.679      ;
; 9.924  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.543      ;
; 9.955  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.512      ;
; 9.989  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.478      ;
; 10.119 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.349      ;
; 10.127 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.341      ;
; 10.215 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 7.253      ;
; 10.415 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 7.052      ;
; 10.475 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 6.992      ;
; 10.533 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 6.934      ;
; 10.959 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 6.508      ;
; 11.778 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 5.690      ;
; 11.784 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 5.684      ;
; 11.874 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 5.594      ;
; 12.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.148     ; 5.321      ;
; 12.072 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 5.395      ;
; 12.084 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.148     ; 5.298      ;
; 12.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 5.217      ;
; 12.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 5.194      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                       ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.607 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.820      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.912      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.912      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.911      ;
; -1.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.923      ;
; -1.503 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.925      ;
; -1.485 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.942      ;
; -1.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.944      ;
; -1.475 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.942      ;
; -1.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.139      ; 0.944      ;
; -1.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.957      ;
; -1.469 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.959      ;
; -1.466 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.951      ;
; -1.463 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 0.965      ;
; -1.461 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.966      ;
; -1.461 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.956      ;
; -1.460 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.967      ;
; -1.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.968      ;
; -1.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.968      ;
; -1.456 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.971      ;
; -1.449 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.978      ;
; -1.448 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.979      ;
; -1.444 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.973      ;
; -1.437 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.990      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.994      ;
; -1.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.996      ;
; -1.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.000      ;
; -1.427 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.990      ;
; -1.422 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.995      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.007      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.996      ;
; -1.419 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.008      ;
; -1.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.009      ;
; -1.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.139      ; 1.000      ;
; -1.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.999      ;
; -1.412 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.016      ;
; -1.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.018      ;
; -1.409 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.019      ;
; -1.409 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.018      ;
; -1.407 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.021      ;
; -1.407 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.010      ;
; -1.407 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.010      ;
; -1.405 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.012      ;
; -1.404 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.013      ;
; -1.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.029      ;
; -1.396 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.032      ;
; -1.396 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.032      ;
; -1.393 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.034      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.025      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.035      ;
; -1.391 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.037      ;
; -1.391 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.036      ;
; -1.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.037      ;
; -1.389 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.039      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.041      ;
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.045      ;
; -1.381 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.036      ;
; -1.380 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.048      ;
; -1.380 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.036      ;
; -1.380 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.036      ;
; -1.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.052      ;
; -1.373 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.044      ;
; -1.370 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.139      ; 1.048      ;
; -1.368 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.060      ;
; -1.363 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.054      ;
; -1.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.055      ;
; -1.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.066      ;
; -1.317 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.110      ;
; -1.309 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.119      ;
; -1.303 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.124      ;
; -1.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.126      ;
; -1.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.139      ; 1.119      ;
; -1.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.117      ;
; -1.295 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.122      ;
; -1.284 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.144      ;
; -1.282 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.145      ;
; -1.276 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.140      ;
; -1.274 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 1.142      ;
; -1.254 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.163      ;
; -1.241 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.187      ;
; -1.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.149      ; 1.243      ;
; 0.362  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                     ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.675 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.263      ;
; 0.395  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.174     ; 1.343      ;
; 0.406  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.639      ;
; 0.408  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.641      ;
; 0.410  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.643      ;
; 0.594  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.828      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.829      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.829      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.830      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.830      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.830      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.829      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.831      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.832      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.600  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.834      ;
; 0.600  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.833      ;
; 0.601  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.835      ;
; 0.601  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.834      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.611  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.845      ;
; 0.616  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.849      ;
; 0.621  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 0.855      ;
; 0.882  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.116      ;
; 0.882  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.115      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.117      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.117      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.118      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.119      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.119      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.116      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.887  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.120      ;
; 0.887  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.120      ;
; 0.888  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.121      ;
; 0.888  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.122      ;
; 0.889  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.123      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.894  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.128      ;
; 0.894  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.128      ;
; 0.895  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.129      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.127      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.897  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.130      ;
; 0.898  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.132      ;
; 0.898  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.131      ;
; 0.899  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.133      ;
; 0.900  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.134      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.904  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.137      ;
; 0.915  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.148      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.215      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.214      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.217      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.216      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.218      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.217      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.216      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.219      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.220      ;
; 0.992  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.226      ;
; 0.992  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.225      ;
; 0.993  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.227      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.228      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.229      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.229      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.226      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.227      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.227      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.231      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.230      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.230      ;
; 0.998  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.232      ;
; 0.999  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.233      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.004  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.238      ;
; 1.005  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.063      ; 1.239      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.060      ; 1.237      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.239      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                                 ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.346 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.935      ;
; 0.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.936      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.936      ;
; 0.351 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.940      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.409      ; 0.964      ;
; 0.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.942      ;
; 0.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.942      ;
; 0.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.945      ;
; 0.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 0.947      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff          ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[287]                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; paddle_mode_reg                                                                                                                                                                            ; paddle_mode_reg                                                                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                               ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                             ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.362 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|sdram_rdy                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_request_reg                                     ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sdram_ctrl:sdram_controller|r_wr_act                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.373 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.608      ;
; 0.424 ; seq_reg[11]                                           ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.659      ;
; 0.433 ; seq_reg[5]                                            ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.668      ;
; 0.435 ; seq_reg[8]                                            ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.670      ;
; 0.468 ; seq_reg[7]                                            ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.703      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.756      ;
; 0.545 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.780      ;
; 0.556 ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.791      ;
; 0.556 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.791      ;
; 0.557 ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.792      ;
; 0.582 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.817      ;
; 0.584 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.819      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.823      ;
; 0.588 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.823      ;
; 0.589 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.824      ;
; 0.590 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.825      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.606 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.841      ;
; 0.611 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.846      ;
; 0.618 ; sdram_ctrl:sdram_controller|r_rd_act                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.853      ;
; 0.620 ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.855      ;
; 0.628 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.863      ;
; 0.632 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.867      ;
; 0.636 ; seq_reg[10]                                           ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.871      ;
; 0.642 ; sdram_request_complete_reg                            ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.877      ;
; 0.731 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.966      ;
; 0.732 ; seq_reg[6]                                            ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.966      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.976      ;
; 0.754 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.989      ;
; 0.809 ; seq_reg[4]                                            ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 1.045      ;
; 0.812 ; sdram_ctrl:sdram_controller|r_wr_act                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.047      ;
; 0.819 ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.054      ;
; 0.820 ; sdram_ctrl:sdram_controller|r_rd_reg                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.055      ;
; 0.830 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.065      ;
; 0.848 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.083      ;
; 0.862 ; seq_reg[2]                                            ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.097      ;
; 0.869 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.104      ;
; 0.874 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.109      ;
; 0.876 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.111      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.112      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.112      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.879 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.114      ;
; 0.879 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.114      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.116      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.122      ;
; 0.888 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.123      ;
; 0.890 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.125      ;
; 0.890 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.125      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.909 ; sdram_ctrl:sdram_controller|r_refr_req                ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.144      ;
; 0.931 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.166      ;
; 0.940 ; seq_reg[9]                                            ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.177      ;
; 0.957 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.194      ;
; 0.962 ; seq_reg[4]                                            ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.197      ;
; 0.972 ; seq_reg[0]                                            ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.207      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.208      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.211      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.212      ;
; 0.984 ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.219      ;
; 0.986 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.221      ;
; 0.987 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.222      ;
; 0.987 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.222      ;
; 0.987 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.222      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.223      ;
; 0.989 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.226      ;
; 0.989 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.224      ;
; 0.989 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.224      ;
; 0.997 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.232      ;
; 0.998 ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.233      ;
; 1.000 ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.235      ;
; 1.000 ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.235      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_wr_reg                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.053      ; 1.246      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.261      ;
; 1.033 ; sdram_request_reg                                     ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.073      ; 1.277      ;
; 1.038 ; seq_reg[0]                                            ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.272      ;
; 1.047 ; seq_reg[9]                                            ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.284      ;
; 1.048 ; sdram_ctrl:sdram_controller|r_refr_act                ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.283      ;
; 1.061 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.296      ;
; 1.064 ; seq_reg[10]                                           ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.303      ;
; 1.080 ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.060      ; 1.311      ;
; 1.086 ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.321      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.322      ;
; 1.096 ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.331      ;
; 1.097 ; sdram_ctrl:sdram_controller|r_psel[0]                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.334      ;
+-------+-------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.362 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 0.597      ;
; 0.603 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 0.838      ;
; 0.813 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.047      ;
; 0.839 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.074      ;
; 0.899 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.133      ;
; 0.910 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.144      ;
; 0.910 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.145      ;
; 0.933 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.167      ;
; 0.933 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.168      ;
; 0.937 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.171      ;
; 1.070 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.305      ;
; 1.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 1.599      ;
; 1.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 1.600      ;
; 1.205 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.439      ;
; 1.247 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 1.670      ;
; 1.248 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 1.671      ;
; 1.265 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 1.688      ;
; 1.308 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.543      ;
; 1.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.151      ; 1.825      ;
; 1.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 1.852      ;
; 1.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 1.852      ;
; 1.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 1.852      ;
; 1.473 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 1.895      ;
; 1.668 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.903      ;
; 1.679 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.914      ;
; 1.708 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.943      ;
; 1.719 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.954      ;
; 1.740 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.164      ;
; 1.791 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.224      ;
; 1.876 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.309      ;
; 1.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.323      ;
; 1.911 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.344      ;
; 1.930 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 2.352      ;
; 1.930 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 2.352      ;
; 1.937 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.370      ;
; 1.939 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.372      ;
; 1.965 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.398      ;
; 1.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.420      ;
; 1.991 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 2.226      ;
; 2.002 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 2.237      ;
; 2.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.429      ;
; 2.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.435      ;
; 2.056 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.491      ;
; 2.057 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.492      ;
; 2.070 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.505      ;
; 2.110 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.534      ;
; 2.121 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.545      ;
; 2.123 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.547      ;
; 2.125 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.558      ;
; 2.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.559      ;
; 2.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.577      ;
; 2.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.614      ;
; 2.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.615      ;
; 2.208 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.641      ;
; 2.210 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.643      ;
; 2.220 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.644      ;
; 2.231 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.655      ;
; 2.262 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.695      ;
; 2.276 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.700      ;
; 2.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.707      ;
; 2.292 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.725      ;
; 2.292 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.725      ;
; 2.308 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.741      ;
; 2.314 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.738      ;
; 2.318 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.751      ;
; 2.328 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.752      ;
; 2.333 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.757      ;
; 2.341 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.776      ;
; 2.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.774      ;
; 2.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.782      ;
; 2.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.805      ;
; 2.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.810      ;
; 2.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.835      ;
; 2.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.835      ;
; 2.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.830      ;
; 2.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.861      ;
; 2.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.870      ;
; 2.444 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 2.679      ;
; 2.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.886      ;
; 2.455 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.879      ;
; 2.460 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.884      ;
; 2.462 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.886      ;
; 2.481 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.905      ;
; 2.488 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.912      ;
; 2.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.920      ;
; 2.516 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.940      ;
; 2.545 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.980      ;
; 2.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 2.996      ;
; 2.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 2.996      ;
; 2.565 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 2.989      ;
; 2.572 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.005      ;
; 2.580 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.013      ;
; 2.582 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.019      ;
; 2.585 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 3.009      ;
; 2.586 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.023      ;
; 2.593 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 3.026      ;
; 2.604 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.143      ; 3.028      ;
; 2.606 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.156      ; 3.043      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.346     ; 0.919      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.167 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 3.162      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
; -2.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.086      ; 3.054      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.334 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.878      ; 3.977      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.881      ; 3.979      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
; -0.333 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.876      ; 3.974      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                           ;
+-------+---------------------------------------+---------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.016 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.485      ;
; 8.026 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.475      ;
; 8.026 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.475      ;
; 8.026 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.475      ;
; 8.026 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.475      ;
; 8.026 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.475      ;
; 8.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.441      ;
; 8.088 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 3.414      ;
; 8.088 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 3.414      ;
; 8.424 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.067      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[14]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[14]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[18]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[18]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[24]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[24]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[11]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[19]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[19]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.431 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 3.068      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.054      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.054      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.054      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.054      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.054      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 3.064      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[30]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[31]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.065      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.063      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[0]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[1]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[2]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[3]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[4]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[5]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[6]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[8]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[9]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[10]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.060      ;
+-------+---------------------------------------+---------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.258     ; 2.941      ;
; 8.412 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 2.959      ;
; 8.412 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 2.959      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 2.942      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 2.942      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 2.935      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 2.934      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.933      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.932      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 2.942      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 2.942      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 2.932      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.933      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 2.933      ;
; 8.425 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 2.942      ;
; 8.427 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 2.944      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.307     ; 2.795      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 2.799      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 2.799      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.320     ; 2.782      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 2.799      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.305     ; 2.797      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.305     ; 2.797      ;
; 8.435 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.315     ; 2.787      ;
; 8.436 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.315     ; 2.786      ;
; 8.436 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.314     ; 2.787      ;
; 8.436 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.315     ; 2.786      ;
; 8.436 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.315     ; 2.786      ;
; 8.437 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.316     ; 2.784      ;
; 8.437 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.316     ; 2.784      ;
; 8.437 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.316     ; 2.784      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.899      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.899      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.899      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 2.897      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 2.887      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 2.895      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 2.897      ;
; 8.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 2.882      ;
; 8.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.207     ; 2.887      ;
; 8.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 2.886      ;
; 8.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 2.886      ;
; 8.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 2.886      ;
; 8.453 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 2.884      ;
; 8.453 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 2.884      ;
; 8.453 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.209     ; 2.884      ;
; 8.559 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.942      ;
; 8.559 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.942      ;
; 8.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.722      ;
; 8.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.722      ;
; 8.648 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.722      ;
; 8.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 2.722      ;
; 8.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 2.711      ;
; 8.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 2.722      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.598      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.597      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.597      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.597      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.597      ;
; 8.902 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.599      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 2.601      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 2.586      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 2.586      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 2.586      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 2.586      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.577      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.576      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.576      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.577      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.576      ;
; 8.904 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 2.577      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 3.989      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
; 13.376 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.164     ; 3.990      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.253 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.601      ; 3.685      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.603      ; 3.688      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
; -0.252 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.683      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.302 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.139      ; 2.837      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
; 0.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.150      ; 2.949      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.309      ; 1.820      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.315      ; 2.105      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.147      ; 2.836      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.147      ; 2.836      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.147      ; 2.836      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.141      ; 2.830      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
; 2.407 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.144      ; 2.833      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.442      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.441      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.441      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.441      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.432      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 2.441      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.432      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.432      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.432      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.443      ;
; 2.014 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.447      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.128      ; 2.423      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.132      ; 2.427      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.015 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.127      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.016 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.126      ; 2.422      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 2.572      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 2.572      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 2.572      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.100      ; 2.561      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 2.572      ;
; 2.255 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.111      ; 2.572      ;
; 2.358 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.787      ;
; 2.358 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.787      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.277 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.697      ;
; 3.277 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.697      ;
; 3.277 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.697      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.138      ; 3.697      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.138      ; 3.697      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.138      ; 3.697      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
; 3.278 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.139      ; 3.698      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.599 ; 5.817        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.733 ; 5.848        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.801 ; 5.897        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.848 ; 5.848        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.897 ; 5.897        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.670  ; 8.785        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.679  ; 8.865        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.738  ; 8.834        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.827  ; 8.827        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.370  ; 10.390       ; 1.020          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                             ;
; 9.423  ; 10.443       ; 1.020          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                             ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                    ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                            ;
; 10.116 ; 10.334       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                            ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                                        ;
; 10.118 ; 10.336       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                                        ;
; 10.129 ; 10.347       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                          ;
; 10.131 ; 10.349       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                          ;
; 10.131 ; 10.349       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                          ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed                          ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110          ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError                    ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]                        ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]                        ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]                        ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]                        ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]                         ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[1]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[2]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[1]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[2]                           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01     ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10     ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11     ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB              ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000           ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]                   ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]                ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~_Duplicate_1  ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~_Duplicate_1  ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut                  ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]               ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]               ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.282 ; 17.612       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.287 ; 17.617       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]       ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[0]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt              ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                 ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[0]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[1]         ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]         ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]          ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq             ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq           ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq               ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.605 ; 17.605       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.643  ; 99.844       ; 10.201         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.954  ; 100.155      ; 10.201         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.827  ; 99.827       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.844  ; 99.844       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.856  ; 99.856       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.857  ; 99.857       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.915  ; 100.133      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.440 ; 2.611 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.425 ; 2.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.427 ; 2.598 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.425 ; 2.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.375 ; 2.545 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.434 ; 2.605 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.440 ; 2.611 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 2.895 ; 3.129 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.673 ; 0.844 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.688 ; 0.859 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.691 ; 0.862 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.677 ; 0.848 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.649 ; -1.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.650 ; -1.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.649 ; -1.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.657 ; -1.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.664 ; -1.835 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.051 ; -2.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.122 ; -0.293 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.138 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.141 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.126 ; -0.297 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.697  ; 2.547  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.006  ; 1.949  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.017  ; 1.960  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.020  ; 1.963  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.355  ; 4.688  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.355  ; 4.688  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.164  ; 2.127  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.887  ; 2.766  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.007  ; 2.944  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.340  ; 4.673  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.928  ; 5.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 5.707  ; 5.953  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.412  ; 4.297  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.391  ; 3.284  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.404  ; 3.303  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.489  ; 3.628  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 6.386  ; 6.569  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.386  ; 4.199  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.386  ; 6.569  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.200  ; 4.055  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.642  ; 4.464  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 6.819  ; 6.936  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.644  ; 4.430  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.728  ; 4.513  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.744  ; 4.525  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.819  ; 6.936  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.292 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.494 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 5.464  ; 5.642  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.467  ; 3.275  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.464  ; 5.642  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.262  ; 3.107  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.886  ; 3.727  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 5.869  ; 5.985  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.721  ; 3.501  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.786  ; 3.606  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.809  ; 3.617  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.869  ; 5.985  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.820  ; 3.841  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.676  ; 3.639  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.863  ; 6.196  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.688  ; 3.651  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.035  ; 1.888  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.034  ; 1.887  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.250  ; 4.428  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.260  ; 4.438  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.382  ; 1.325  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.526  ; 1.488  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.718  ; 4.050  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.526  ; 1.488  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.222  ; 2.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.341  ; 2.280  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.703  ; 4.035  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.035  ; 1.888  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.264  ; 4.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 4.919  ; 5.166  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 3.587  ; 3.473  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.606  ; 2.501  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.619  ; 2.519  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.699  ; 2.835  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.313  ; 3.164  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.493  ; 3.303  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.501  ; 5.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.313  ; 3.164  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.556  ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.669  ; 3.451  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.739  ; 3.523  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.669  ; 3.451  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.682  ; 3.460  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.915  ; 6.031  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.583 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.788 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.484  ; 2.331  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.681  ; 2.492  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.686  ; 4.866  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.484  ; 2.331  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.012  ; 2.862  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 2.924  ; 2.709  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.924  ; 2.709  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.984  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.006  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.075  ; 5.195  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.408  ; 3.428  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.265  ; 3.227  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.452  ; 5.784  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.276  ; 3.238  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.306 ; 3.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.306 ; 3.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.306 ; 3.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.306 ; 3.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.388 ; 5.651 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.698 ; 5.961 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.844 ; 3.734 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.821 ; 3.711 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.203 ; 4.075 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.304 ; 4.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.069 ; 6.332 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.686 ; 3.637 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.686 ; 3.637 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.686 ; 3.637 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.722 ; 5.985 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.661 ; 3.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.661 ; 3.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.424 ; 3.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.550 ; 5.501 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.006 ; 4.896 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.908 ; 8.171 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.626 ; 4.516 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.555 ; 2.506 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.555 ; 2.506 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.555 ; 2.506 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.555 ; 2.506 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.636 ; 4.899 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.934 ; 5.197 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.066 ; 2.956 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.044 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.370 ; 3.242 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.513 ; 3.464 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.290 ; 5.553 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.920 ; 2.871 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.920 ; 2.871 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.920 ; 2.871 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.957 ; 5.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.896 ; 2.847 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.896 ; 2.847 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.621 ; 2.493 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.996 ; 4.947 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.469 ; 4.359 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.341 ; 7.604 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.104 ; 3.994 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.240     ; 3.289     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.240     ; 3.289     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.240     ; 3.289     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.240     ; 3.289     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.626     ; 5.363     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.922     ; 5.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.678     ; 3.788     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.646     ; 3.756     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.951     ; 4.079     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.199     ; 4.248     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.290     ; 6.027     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.610     ; 3.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.610     ; 3.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.610     ; 3.659     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.956     ; 5.693     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.583     ; 3.632     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.583     ; 3.632     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.256     ; 3.384     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.429     ; 5.478     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.833     ; 4.943     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.080     ; 7.817     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.467     ; 4.577     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.489     ; 2.538     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.489     ; 2.538     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.489     ; 2.538     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.489     ; 2.538     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.875     ; 4.612     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.159     ; 4.896     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.903     ; 3.013     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.872     ; 2.982     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.123     ; 3.251     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.410     ; 3.459     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.513     ; 5.250     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.845     ; 2.894     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.845     ; 2.894     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.845     ; 2.894     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.192     ; 4.929     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.819     ; 2.868     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.819     ; 2.868     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.455     ; 2.583     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.877     ; 4.926     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.299     ; 4.409     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.517     ; 7.254     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.947     ; 4.057     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.896 ; -143.821      ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.171 ; -7.116        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -0.151 ; -0.151        ;
; FPGA_CLK                                                                            ; 0.387  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.237  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 7.079  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.057 ; -77.623       ;
; FPGA_CLK                                                                            ; -0.639 ; -0.639        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.135  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 11.423 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.220 ; -10.980       ;
; FPGA_CLK                                                                            ; 0.177  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.629  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.776  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 15.109 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.363 ; -9.438        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.033  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.722  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.086  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.780  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.801  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.593  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.380  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.338 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.591      ;
; -1.854 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.549      ;
; -1.797 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.492      ;
; -1.792 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.487      ;
; -1.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.478      ;
; -1.781 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.476      ;
; -1.776 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.471      ;
; -1.764 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.270     ; 0.452      ;
; -1.760 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.455      ;
; -1.759 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.454      ;
; -1.694 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.277     ; 0.375      ;
; -1.693 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.277     ; 0.374      ;
; -1.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.375      ;
; -1.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.373      ;
; -1.682 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.558      ;
; -1.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.262     ; 0.373      ;
; -1.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.372      ;
; -1.664 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.548      ;
; -1.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.076     ; 0.543      ;
; -1.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.471      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.492      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.492      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.490      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.490      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.489      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.479      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.459      ;
; -1.596 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.459      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.458      ;
; -1.593 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.477      ;
; -1.591 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.475      ;
; -1.589 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.465      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.472      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.470      ;
; -1.585 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.468      ;
; -1.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.465      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.464      ;
; -1.578 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.461      ;
; -1.577 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.460      ;
; -1.576 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.460      ;
; -1.575 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.459      ;
; -1.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.449      ;
; -1.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.445      ;
; -1.535 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.395      ;
; -1.535 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.398      ;
; -1.533 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.396      ;
; -1.533 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.396      ;
; -1.531 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.391      ;
; -1.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.386      ;
; -1.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.386      ;
; -1.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.386      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.386      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.386      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.388      ;
; -1.521 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.385      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.384      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.387      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.387      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.387      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.384      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.385      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.384      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.399      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.384      ;
; -1.515 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.398      ;
; -1.514 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.385      ;
; -1.514 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.398      ;
; -1.514 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.385      ;
; -1.513 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.384      ;
; -1.513 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.396      ;
; -1.512 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.396      ;
; -1.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.373      ;
; -1.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.398      ;
; -1.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.397      ;
; -1.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.372      ;
; -1.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.372      ;
; -1.503 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.374      ;
; -1.503 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.386      ;
; -1.503 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.373      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.372      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.395      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.395      ;
; -1.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.384      ;
; -1.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.384      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.374      ;
; -1.496 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.373      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.385      ;
; -1.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.374      ;
; -1.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.384      ;
; -1.490 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.373      ;
; -1.489 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.074     ; 0.373      ;
; 6.658  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.896      ;
; 6.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.802      ;
; 6.756  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.798      ;
; 6.760  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.794      ;
; 6.775  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.779      ;
; 6.834  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 4.720      ;
; 6.840  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 4.713      ;
; 6.841  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.710      ;
; 6.841  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 4.710      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.691      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.689      ;
; -0.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.681      ;
; -0.150 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.670      ;
; -0.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.662      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.661      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.666      ;
; -0.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.655      ;
; -0.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.655      ;
; -0.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.652      ;
; -0.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.658      ;
; -0.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.657      ;
; -0.128 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.648      ;
; -0.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.647      ;
; -0.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.641      ;
; -0.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.641      ;
; -0.126 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.639      ;
; -0.120 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.640      ;
; -0.119 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.629      ; 0.634      ;
; -0.118 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.632      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.631      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.637      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.636      ;
; -0.116 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.629      ; 0.631      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.634      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.628      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.627      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.627      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.628      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.626      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.626      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.625      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.631      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.629      ; 0.626      ;
; -0.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.630      ;
; -0.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.623      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.627      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.627      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.626      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.625      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.625      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.624      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.624      ;
; -0.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.621      ;
; -0.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.620      ;
; -0.098 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.618      ;
; -0.098 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.618      ;
; -0.097 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.617      ;
; -0.095 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.615      ;
; -0.094 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.614      ;
; -0.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.569      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.559      ;
; -0.042 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.556      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.559      ;
; -0.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.559      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.551      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.557      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.549      ;
; -0.033 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.547      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.549      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.547      ;
; -0.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.540      ;
; -0.015 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.535      ;
; -0.014 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.535      ;
; -0.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.531      ;
; -0.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.531      ;
; -0.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.530      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.529      ;
; -0.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.530      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.527      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.526      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.526      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.527      ;
; -0.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.525      ;
; -0.005 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.525      ;
; 0.059  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.461      ;
; 8.318  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.344     ; 2.940      ;
; 8.420  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 2.837      ;
; 8.537  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.159     ; 2.906      ;
; 8.818  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.166     ; 2.618      ;
; 8.981  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.459      ;
; 8.991  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.166     ; 2.445      ;
; 9.040  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.163     ; 2.399      ;
; 9.054  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.386      ;
; 9.112  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.325      ;
; 9.115  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.322      ;
; 9.119  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.166     ; 2.317      ;
; 9.161  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.163     ; 2.278      ;
; 9.177  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.926      ; 3.153      ;
; 9.210  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.925      ; 3.119      ;
; 9.221  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.926      ; 3.109      ;
; 9.224  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.925      ; 3.105      ;
; 9.226  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.214      ;
; 9.239  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.166     ; 2.197      ;
; 9.275  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.162      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.151 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -0.918     ; 0.538      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.387   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.088      ;
; 197.883 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.103      ; 2.207      ;
; 197.903 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.158     ; 0.808      ;
; 198.369 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.582      ;
; 198.373 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.578      ;
; 198.437 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.514      ;
; 198.441 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.510      ;
; 198.441 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.510      ;
; 198.445 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.506      ;
; 198.453 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.498      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.459 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.046     ; 1.482      ;
; 198.491 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.460      ;
; 198.505 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.446      ;
; 198.506 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.445      ;
; 198.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.442      ;
; 198.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.442      ;
; 198.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.441      ;
; 198.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.438      ;
; 198.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.430      ;
; 198.521 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.430      ;
; 198.557 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.394      ;
; 198.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.392      ;
; 198.568 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.383      ;
; 198.572 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.379      ;
; 198.573 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.378      ;
; 198.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.377      ;
; 198.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.374      ;
; 198.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.374      ;
; 198.578 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.373      ;
; 198.581 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.370      ;
; 198.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.362      ;
; 198.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.362      ;
; 198.589 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.362      ;
; 198.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.326      ;
; 198.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.326      ;
; 198.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.324      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.047     ; 1.309      ;
; 198.636 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.315      ;
; 198.640 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.311      ;
; 198.641 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.310      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.309      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.308      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.306      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.306      ;
; 198.646 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.305      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.304      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.302      ;
; 198.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.294      ;
; 198.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.294      ;
; 198.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.294      ;
; 198.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.294      ;
; 198.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.258      ;
; 198.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.258      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.256      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.256      ;
; 198.704 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.247      ;
; 198.708 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.243      ;
; 198.709 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.242      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.241      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.241      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.240      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.238      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.238      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.237      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.237      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.236      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.234      ;
; 198.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.226      ;
; 198.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.226      ;
; 198.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.226      ;
; 198.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.226      ;
; 198.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.226      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.190      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.190      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.190      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.188      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.188      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                ;
+-------+-------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.237 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.350      ;
; 3.237 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.350      ;
; 3.285 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.302      ;
; 3.285 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.302      ;
; 3.361 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 2.245      ;
; 3.515 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.131      ;
; 3.524 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.122      ;
; 3.541 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.105      ;
; 3.542 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.104      ;
; 3.549 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.097      ;
; 3.550 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.096      ;
; 3.570 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.016      ;
; 3.570 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.016      ;
; 3.573 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 2.028      ;
; 3.595 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 1.993      ;
; 3.605 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 1.983      ;
; 3.618 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.968      ;
; 3.618 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.968      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.627 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.017      ;
; 3.643 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 1.945      ;
; 3.653 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 1.935      ;
; 3.665 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.980      ;
; 3.666 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.979      ;
; 3.667 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.978      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.673 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.972      ;
; 3.681 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.964      ;
; 3.684 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.920      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.694 ; SDRAM_READ_ENABLE       ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.950      ;
; 3.712 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.880      ;
; 3.736 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.908      ;
; 3.751 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.841      ;
; 3.760 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.841      ;
; 3.763 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.829      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.777 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.868      ;
; 3.788 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.810      ;
; 3.801 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.785      ;
; 3.817 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.828      ;
; 3.818 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.826      ;
; 3.819 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.826      ;
; 3.820 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.824      ;
; 3.822 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.822      ;
; 3.824 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.820      ;
; 3.826 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.818      ;
; 3.849 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.737      ;
; 3.856 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 1.738      ;
; 3.859 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.747      ;
; 3.875 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.727      ;
; 3.877 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.718      ;
; 3.877 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.718      ;
; 3.877 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.725      ;
; 3.881 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.712      ;
; 3.889 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.704      ;
; 3.895 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 1.699      ;
; 3.904 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 1.690      ;
; 3.925 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.670      ;
; 3.925 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.670      ;
; 3.982 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.611      ;
; 4.006 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 1.583      ;
; 4.029 ; SDRAM_ADDR[4]           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.579      ;
; 4.040 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.560      ;
; 4.075 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.520      ;
; 4.091 ; SDRAM_REQUEST           ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 1.570      ;
; 4.101 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.551      ;
; 4.126 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.477      ;
; 4.133 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.097     ; 1.540      ;
; 4.137 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.455      ;
; 4.137 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.455      ;
; 4.185 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.407      ;
; 4.185 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.407      ;
; 4.218 ; SDRAM_DI[10]            ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.435      ;
; 4.219 ; SDRAM_DI[2]             ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.433      ;
; 4.236 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.359      ;
+-------+-------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.079  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -0.917     ; 0.652      ;
; 10.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.071      ;
; 10.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.058      ;
; 10.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.056      ;
; 10.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.054      ;
; 10.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.043      ;
; 10.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.041      ;
; 10.418 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 7.003      ;
; 10.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.995      ;
; 10.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.988      ;
; 10.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.986      ;
; 10.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.982      ;
; 10.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.927      ;
; 10.525 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.896      ;
; 10.538 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.883      ;
; 10.593 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.828      ;
; 10.662 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.759      ;
; 10.677 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.744      ;
; 10.679 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.742      ;
; 10.738 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.683      ;
; 10.777 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.643      ;
; 10.790 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.630      ;
; 10.834 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.599      ;
; 10.837 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.584      ;
; 10.845 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.575      ;
; 10.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.586      ;
; 10.856 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.565      ;
; 10.860 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.561      ;
; 10.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.550      ;
; 10.873 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.548      ;
; 10.875 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.546      ;
; 10.877 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.544      ;
; 10.902 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.531      ;
; 10.932 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.489      ;
; 10.936 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.485      ;
; 11.031 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.390      ;
; 11.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.386      ;
; 11.089 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.331      ;
; 11.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.277      ;
; 11.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.287      ;
; 11.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.262      ;
; 11.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.260      ;
; 11.220 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.201      ;
; 11.283 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.137      ;
; 11.287 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 6.133      ;
; 11.319 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 6.102      ;
; 11.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.093      ;
; 11.344 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 6.089      ;
; 11.571 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 5.849      ;
; 11.628 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 5.805      ;
; 12.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 5.416      ;
; 12.020 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 5.401      ;
; 12.022 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 5.399      ;
; 12.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 5.340      ;
; 12.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 5.241      ;
; 12.432 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 4.988      ;
; 12.489 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 4.944      ;
; 12.675 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.808      ;
; 12.688 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.795      ;
; 12.722 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.761      ;
; 12.735 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.748      ;
; 12.743 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.740      ;
; 12.757 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.726      ;
; 12.770 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.713      ;
; 12.790 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.693      ;
; 12.825 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.658      ;
; 12.846 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.636      ;
; 12.859 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.623      ;
; 12.914 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.568      ;
; 12.987 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.496      ;
; 13.034 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.449      ;
; 13.069 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.414      ;
; 13.149 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.333      ;
; 13.158 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.324      ;
; 13.162 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.320      ;
; 13.181 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.302      ;
; 13.185 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.298      ;
; 13.217 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.265      ;
; 13.228 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.255      ;
; 13.232 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.251      ;
; 13.263 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.220      ;
; 13.267 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.216      ;
; 13.352 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.130      ;
; 13.356 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.126      ;
; 13.461 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 4.021      ;
; 13.469 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 4.014      ;
; 13.516 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 3.967      ;
; 13.551 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 3.932      ;
; 13.640 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 3.842      ;
; 13.655 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 3.827      ;
; 13.659 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 3.823      ;
; 13.943 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 3.539      ;
; 14.330 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 3.153      ;
; 14.377 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 3.106      ;
; 14.412 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.035     ; 3.071      ;
; 14.465 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.965      ;
; 14.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.961      ;
; 14.501 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.036     ; 2.981      ;
; 14.547 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 2.881      ;
; 14.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 2.877      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                              ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.057 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.405      ;
; -1.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.440      ;
; -1.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.440      ;
; -1.021 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.440      ;
; -1.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.449      ;
; -1.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.452      ;
; -1.002 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.459      ;
; -0.999 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.463      ;
; -0.999 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.462      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.463      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.463      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.457      ;
; -0.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.465      ;
; -0.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.465      ;
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.465      ;
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.466      ;
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.465      ;
; -0.991 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.470      ;
; -0.991 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.470      ;
; -0.990 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.465      ;
; -0.987 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.468      ;
; -0.986 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.475      ;
; -0.984 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.471      ;
; -0.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.483      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.478      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.484      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.487      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                    ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.482      ;
; -0.970 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.491      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.493      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.494      ;
; -0.967 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.487      ;
; -0.966 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.489      ;
; -0.966 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.489      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.492      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.498      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.499      ;
; -0.961 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.500      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.501      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.495      ;
; -0.959 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.502      ;
; -0.959 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.495      ;
; -0.959 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.495      ;
; -0.958 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.497      ;
; -0.956 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.505      ;
; -0.955 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.507      ;
; -0.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.508      ;
; -0.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.509      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.511      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.512      ;
; -0.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.515      ;
; -0.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.514      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.510      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.516      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.510      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.510      ;
; -0.944 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.511      ;
; -0.939 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.515      ;
; -0.939 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.522      ;
; -0.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.517      ;
; -0.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.523      ;
; -0.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.522      ;
; -0.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.528      ;
; -0.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.526      ;
; -0.927 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.534      ;
; -0.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.268      ; 0.545      ;
; -0.913 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.548      ;
; -0.911 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.550      ;
; -0.911 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.550      ;
; -0.908 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.547      ;
; -0.907 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.548      ;
; -0.904 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.551      ;
; -0.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.561      ;
; -0.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.561      ;
; -0.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.561      ;
; -0.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.561      ;
; -0.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.573      ;
; -0.876 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.585      ;
; -0.859 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.602      ;
; 0.168  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.491      ;
; 0.176  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.499      ;
; 0.177  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.500      ;
; 0.177  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.226      ; 0.507      ;
; 0.179  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.502      ;
; 0.181  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.503      ;
; 0.181  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.504      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|SIERxWEn                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|SIERxWEn                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.639 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 1.769      ;
; 0.188  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.103     ; 0.691      ;
; 0.195  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.314      ;
; 0.197  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.316      ;
; 0.206  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.325      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.309  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.428      ;
; 0.312  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.431      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.575      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.578      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.467  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.586      ;
; 0.470  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.589      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.630      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.633      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.523  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.641      ;
; 0.523  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.642      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.642      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.526  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.034      ; 0.644      ;
; 0.526  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.645      ;
; 0.527  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.646      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.462      ;
; 0.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.463      ;
; 0.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.464      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.467      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.469      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.235      ; 0.484      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.471      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.473      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.474      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.473      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.476      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.476      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.475      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.477      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.479      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.478      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.480      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.486      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.484      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.487      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.487      ;
; 0.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.491      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.495      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.491      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.493      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.500      ;
; 0.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.495      ;
; 0.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.496      ;
; 0.172 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.495      ;
; 0.176 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.499      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.509      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.510      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.181 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.512      ;
; 0.183 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.227      ; 0.514      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.508      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[3]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[2]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[4]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[0]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[0]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[5]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[6]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[7]                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.205 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.210 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.331      ;
; 0.212 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.332      ;
; 0.232 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.352      ;
; 0.257 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.262 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.383      ;
; 0.274 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.394      ;
; 0.279 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.400      ;
; 0.283 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.404      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.303 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.424      ;
; 0.307 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.428      ;
; 0.311 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.431      ;
; 0.314 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.435      ;
; 0.318 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.438      ;
; 0.319 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.439      ;
; 0.323 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.443      ;
; 0.346 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.466      ;
; 0.365 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.485      ;
; 0.377 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.498      ;
; 0.384 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.504      ;
; 0.388 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.509      ;
; 0.397 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.517      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.530      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.529      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.530      ;
; 0.411 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.532      ;
; 0.419 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.540      ;
; 0.427 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.547      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.563      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.566      ;
; 0.451 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.456 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.579      ;
; 0.464 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.468 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.471 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.591      ;
; 0.479 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.601      ;
; 0.497 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.617      ;
; 0.499 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.619      ;
; 0.500 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.621      ;
; 0.500 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.620      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.626      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.626      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.508 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.634      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.029      ; 0.621      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.629      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.629      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.514 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.634      ;
; 0.515 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.636      ;
; 0.517 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.638      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.639      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.639      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.641      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.642      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.642      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.642      ;
; 0.522 ; seq_reg[9]                                                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.643      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.645      ;
; 0.536 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.040      ; 0.660      ;
; 0.544 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.665      ;
; 0.547 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.664      ;
; 0.549 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.671      ;
; 0.560 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.681      ;
; 0.564 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.685      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.287 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.408      ;
; 0.406 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.526      ;
; 0.417 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.537      ;
; 0.438 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.559      ;
; 0.456 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.576      ;
; 0.460 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.580      ;
; 0.469 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.589      ;
; 0.470 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.590      ;
; 0.484 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.604      ;
; 0.527 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.647      ;
; 0.546 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 0.829      ;
; 0.547 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 0.830      ;
; 0.568 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 0.845      ;
; 0.569 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 0.846      ;
; 0.583 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 0.860      ;
; 0.619 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.739      ;
; 0.641 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.762      ;
; 0.648 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 0.931      ;
; 0.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 0.947      ;
; 0.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 0.947      ;
; 0.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 0.947      ;
; 0.676 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 0.952      ;
; 0.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.101      ;
; 0.839 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.960      ;
; 0.852 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.973      ;
; 0.858 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.979      ;
; 0.871 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.992      ;
; 0.917 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.201      ;
; 0.921 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.205      ;
; 0.922 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.206      ;
; 0.927 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.211      ;
; 0.935 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.211      ;
; 0.935 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.211      ;
; 0.945 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.222      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.247      ;
; 0.976 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.253      ;
; 0.979 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.256      ;
; 0.993 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.270      ;
; 0.997 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.281      ;
; 1.001 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.278      ;
; 1.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.297      ;
; 1.013 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.297      ;
; 1.015 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.292      ;
; 1.016 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.302      ;
; 1.023 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.309      ;
; 1.024 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.308      ;
; 1.039 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 1.160      ;
; 1.042 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.319      ;
; 1.045 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.322      ;
; 1.052 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 1.173      ;
; 1.071 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.348      ;
; 1.080 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.364      ;
; 1.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.365      ;
; 1.083 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.367      ;
; 1.084 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.368      ;
; 1.093 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.370      ;
; 1.097 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.374      ;
; 1.099 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.376      ;
; 1.100 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.377      ;
; 1.108 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.385      ;
; 1.108 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.392      ;
; 1.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.393      ;
; 1.111 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.388      ;
; 1.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.392      ;
; 1.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.420      ;
; 1.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.428      ;
; 1.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.430      ;
; 1.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.431      ;
; 1.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.433      ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.434      ;
; 1.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.430      ;
; 1.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.433      ;
; 1.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.440      ;
; 1.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.443      ;
; 1.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.446      ;
; 1.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.448      ;
; 1.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.458      ;
; 1.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.468      ;
; 1.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.471      ;
; 1.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.496      ;
; 1.213 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.497      ;
; 1.219 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.496      ;
; 1.222 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.499      ;
; 1.226 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 1.346      ;
; 1.229 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.506      ;
; 1.248 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.532      ;
; 1.248 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.534      ;
; 1.251 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.528      ;
; 1.251 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 1.537      ;
; 1.254 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.531      ;
; 1.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.540      ;
; 1.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.543      ;
; 1.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.551      ;
; 1.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.546      ;
; 1.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.090      ; 1.554      ;
; 1.281 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.558      ;
; 1.285 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.562      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.423 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -0.783     ; 0.496      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.220 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 1.741      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
; -1.112 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.628      ; 1.691      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.724      ; 2.300      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.723      ; 2.299      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
; 0.177 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.722      ; 2.298      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.629 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.922      ;
; 9.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.913      ;
; 9.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.913      ;
; 9.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.913      ;
; 9.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.913      ;
; 9.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.913      ;
; 9.652 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.894      ;
; 9.674 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.878      ;
; 9.674 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 1.878      ;
; 9.845 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.700      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.690      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.690      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[26]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.690      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.690      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.690      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[14]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 1.696      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[30]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[31]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.697      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[18]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[18]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[24]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[24]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[5]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[11]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 1.699      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 1.699      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 1.699      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 1.699      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.100     ; 1.695      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[19]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[28]                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 1.700      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.689      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.689      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.689      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.689      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.105     ; 1.689      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
; 9.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.696      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.776  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 1.663      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.675      ;
; 9.813  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.675      ;
; 9.820  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.665      ;
; 9.820  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.665      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.664      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.664      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 1.658      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.666      ;
; 9.821  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.664      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.659      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.659      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 1.657      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 1.657      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.658      ;
; 9.822  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 1.658      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 1.648      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 1.648      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 1.648      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.133     ; 1.639      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.133     ; 1.639      ;
; 9.825  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.133     ; 1.639      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.126     ; 1.645      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.135     ; 1.636      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.126     ; 1.645      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.131     ; 1.640      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.634      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.132     ; 1.639      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.132     ; 1.639      ;
; 9.826  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.132     ; 1.639      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 1.590      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 1.590      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 1.581      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 1.581      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 1.590      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 1.581      ;
; 9.827  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 1.643      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 1.581      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 1.582      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 1.581      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.576      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 1.581      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 1.587      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 1.587      ;
; 9.828  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 1.578      ;
; 9.829  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 1.585      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.705      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.705      ;
; 9.931  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.556      ;
; 9.931  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.556      ;
; 9.931  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.556      ;
; 9.931  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.556      ;
; 9.931  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.556      ;
; 9.932  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.549      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.502      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.503      ;
; 10.046 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.506      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.501      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.501      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.501      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.495      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.501      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.495      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.495      ;
; 10.047 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.495      ;
; 10.048 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.492      ;
; 10.049 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.489      ;
; 10.049 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.489      ;
; 10.049 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.489      ;
; 10.049 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.489      ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.109 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.309      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 2.307      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 2.307      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 2.307      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.308      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.308      ;
; 15.110 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 2.308      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.160      ; 2.047      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.159      ; 2.046      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
; -0.363 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.158      ; 2.045      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.033 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.264      ; 1.606      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
; 0.197 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.660      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.722 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 0.988      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 1.141      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.081      ; 1.598      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.081      ; 1.598      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.609      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.081      ; 1.598      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.609      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.081      ; 1.598      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.081      ; 1.598      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[31]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[20]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[4]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[24]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 1.606      ;
; 1.322 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[31]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.084      ; 1.601      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.086 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 1.369      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.365      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.365      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.365      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.365      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.359      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.356      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.358      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.366      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.355      ;
; 1.087 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.354      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.430      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.430      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.430      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.055      ; 1.424      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.430      ;
; 1.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.061      ; 1.430      ;
; 1.263 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.543      ;
; 1.263 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.543      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 2.054      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 2.054      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 2.054      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
; 1.780 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 2.055      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[9]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.801 ; 5.870        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.824 ; 5.877        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.870 ; 5.870        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.877 ; 5.877        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.625  ; 8.809        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.738  ; 8.807        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.761  ; 8.814        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.805  ; 8.805        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.380  ; 10.390       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 9.431  ; 10.441       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 10.161 ; 10.391       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 10.161 ; 10.391       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                                                                   ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                                                                   ;
; 10.198 ; 10.382       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ;
; 10.198 ; 10.382       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ;
; 10.199 ; 10.383       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                                                                                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[14]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                                                             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a32~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a33~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a35~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_address_reg0          ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_we_reg                         ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_ud41:auto_generated|ram_block1a0~porta_address_reg0                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_ud41:auto_generated|ram_block1a0~porta_we_reg                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~portb_address_reg0          ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_address_reg0         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a39~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_we_reg                       ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~portb_address_reg0         ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.616 ; 17.616       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.338  ; 99.438       ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.462  ; 100.562      ; 10.100         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.438  ; 99.438       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.449  ; 99.449       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.460  ; 99.460       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.462  ; 99.462       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.430 ; 1.981 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.439 ; 1.990 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.431 ; 1.982 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.430 ; 1.981 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.408 ; 1.957 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.435 ; 1.986 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 1.744 ; 2.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.399 ; 0.950 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.411 ; 0.962 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.414 ; 0.965 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.402 ; 0.953 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.982 ; -1.533 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.252 ; -1.766 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.087 ; -0.638 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.651 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.653 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.090 ; -0.641 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 3.420  ; 3.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.643  ; 1.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.206  ; 1.180  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.420  ; 3.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.213  ; 1.187  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.214  ; 1.188  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.066  ; 3.541  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.066  ; 3.541  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.057  ; 3.532  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.289  ; 1.350  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.748  ; 1.744  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.888  ; 1.846  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.054  ; 3.529  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.060  ; 3.535  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.428  ; 3.805  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 3.735  ; 4.293  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 2.456  ; 2.609  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.900  ; 1.968  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.898  ; 1.972  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.085  ; 2.007  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.177  ; 4.628  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.496  ; 2.481  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.177  ; 4.628  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.417  ; 2.397  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.669  ; 2.659  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.385  ; 4.855  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.630  ; 2.627  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.683  ; 2.661  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.691  ; 2.673  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.385  ; 4.855  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.136 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.609 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.545  ; 4.057  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.868  ; 1.913  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.545  ; 4.057  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.776  ; 1.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.110  ; 2.179  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.740  ; 4.267  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.997  ; 2.055  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.033  ; 2.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.042  ; 2.111  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.740  ; 4.267  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.329  ; 2.352  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.171  ; 2.232  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.945  ; 4.420  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.181  ; 2.242  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.682 ; 3.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 3.276 ; 3.830  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 1.978 ; 2.124  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.444 ; 1.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.442 ; 1.512  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 1.621 ; 1.546  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.791 ; 1.783  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.869 ; 1.866  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.553 ; 4.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.791 ; 1.783  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.924 ; 1.932  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.959 ; 1.972  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.995 ; 2.004  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 1.959 ; 1.972  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.965 ; 1.981  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.750 ; 4.232  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.721 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.325 ; 1.359  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.413 ; 1.457  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.094 ; 3.603  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.325 ; 1.359  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.611 ; 1.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.536 ; 1.592  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.536 ; 1.592  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 1.572 ; 1.636  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.580 ; 1.646  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.280 ; 3.806  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.082 ; 2.106  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.934 ; 1.996  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.938 ; 1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.938 ; 1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.938 ; 1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.938 ; 1.937 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.580 ; 4.027 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.749 ; 4.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.156 ; 2.189 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.149 ; 2.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.320 ; 2.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.491 ; 2.490 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.957 ; 4.404 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.151 ; 2.150 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.151 ; 2.150 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.151 ; 2.150 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.771 ; 4.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.140 ; 2.139 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.140 ; 2.139 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.915 ; 1.860 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.211 ; 3.210 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.823 ; 2.856 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.002 ; 5.449 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.628 ; 2.661 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 1.494 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.495 ; 1.494 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.495 ; 1.494 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.495 ; 1.494 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.137 ; 3.584 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.299 ; 3.746 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.699 ; 1.732 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.692 ; 1.725 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.846 ; 1.791 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.026 ; 2.025 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.499 ; 3.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.700 ; 1.699 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.700 ; 1.699 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.700 ; 1.699 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.320 ; 3.767 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.689 ; 1.688 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.689 ; 1.688 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.457 ; 1.402 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.891 ; 2.890 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.512 ; 2.545 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 4.676 ; 5.123 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.326 ; 2.359 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.010     ; 2.011     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.010     ; 2.011     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.010     ; 2.011     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.010     ; 2.011     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.102     ; 3.655     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.291     ; 3.844     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.304     ; 2.271     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.286     ; 2.253     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.397     ; 2.452     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.636     ; 2.637     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.534     ; 4.087     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.257     ; 2.258     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.257     ; 2.258     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.257     ; 2.258     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.320     ; 3.873     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.241     ; 2.242     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.241     ; 2.242     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.954     ; 2.009     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.337     ; 3.338     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.949     ; 2.916     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.594     ; 5.147     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.722     ; 2.689     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.564     ; 1.565     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.564     ; 1.565     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.564     ; 1.565     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.564     ; 1.565     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.656     ; 3.209     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.837     ; 3.390     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.842     ; 1.809     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.824     ; 1.791     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.917     ; 1.972     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.165     ; 2.166     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.070     ; 3.623     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.802     ; 1.803     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.802     ; 1.803     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.802     ; 1.803     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.865     ; 3.418     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.786     ; 1.787     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.786     ; 1.787     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.492     ; 1.547     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.012     ; 3.013     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.635     ; 2.602     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.262     ; 4.815     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.417     ; 2.384     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                   ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Clock                                                                                ; Setup    ; Hold     ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Worst-case Slack                                                                     ; -3.639   ; -1.823   ; -2.376   ; -0.363  ; 5.596               ;
;  FPGA_CLK                                                                            ; 0.075    ; -0.824   ; -0.334   ; -0.363  ; 89.338              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.022    ; 0.186    ; 7.963    ; 1.086   ; 5.596               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.639   ; 0.135    ; 7.625    ; 0.722   ; 17.259              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675   ; 11.423   ; N/A      ; N/A     ; 5.720               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 2.773    ; 0.187    ; 12.961   ; 1.780   ; 8.533               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 17.589              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.298   ; -1.823   ; -2.376   ; 0.033   ; 9.370               ;
; Design-wide TNS                                                                      ; -286.687 ; -130.849 ; -29.809  ; -9.438  ; 0.0                 ;
;  FPGA_CLK                                                                            ; 0.000    ; -0.824   ; -8.670   ; -9.438  ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -274.407 ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675   ; 0.000    ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -11.110  ; -130.025 ; -21.384  ; 0.000   ; 0.000               ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.770 ; 2.949 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.752 ; 2.931 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.755 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.763 ; 2.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.755 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.703 ; 2.881 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.763 ; 2.942 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.770 ; 2.949 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.766 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.292 ; 3.505 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.779 ; 0.958 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.782 ; 0.961 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.982 ; -1.533 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.252 ; -1.766 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.087 ; -0.293 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.090 ; -0.297 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.361  ; 2.340  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 6.385  ; 6.825  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.750  ; 4.724  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.656  ; 3.596  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.675  ; 3.622  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.834  ; 3.905  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.185  ; 7.486  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.788  ; 4.605  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.185  ; 7.486  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.603  ; 4.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.085  ; 4.905  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.628  ; 7.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 5.060  ; 4.871  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.156  ; 4.933  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 5.168  ; 4.946  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.628  ; 7.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.826 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.176 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 6.119  ; 6.475  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.724  ; 3.597  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.119  ; 6.475  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.518  ; 3.407  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.195  ; 4.097  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 6.531  ; 6.860  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.991  ; 3.858  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.068  ; 3.969  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.087  ; 3.981  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.531  ; 6.860  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.261  ; 4.249  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.078  ; 4.057  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.682 ; 3.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 3.276 ; 3.830  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 1.978 ; 2.124  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.444 ; 1.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.442 ; 1.512  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 1.621 ; 1.546  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.791 ; 1.783  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.869 ; 1.866  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.553 ; 4.015  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.791 ; 1.783  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.924 ; 1.932  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.959 ; 1.972  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.995 ; 2.004  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 1.959 ; 1.972  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.965 ; 1.981  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.750 ; 4.232  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.721 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.325 ; 1.359  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.413 ; 1.457  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.094 ; 3.603  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.325 ; 1.359  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.611 ; 1.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.536 ; 1.592  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.536 ; 1.592  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 1.572 ; 1.636  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.580 ; 1.646  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.280 ; 3.806  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.082 ; 2.106  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.934 ; 1.996  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus1       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus1      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus2       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus2      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; CFG_DIN      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus1       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus1      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus2       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus2      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.15e-09 V                   ; 3.18 V              ; -0.0303 V           ; 0.317 V                              ; 0.07 V                               ; 3.25e-10 s                  ; 3.88e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.15e-09 V                  ; 3.18 V             ; -0.0303 V          ; 0.317 V                             ; 0.07 V                              ; 3.25e-10 s                 ; 3.88e-10 s                 ; No                        ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.52e-07 V                   ; 3.14 V              ; -0.0428 V           ; 0.161 V                              ; 0.071 V                              ; 4.71e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 6.52e-07 V                  ; 3.14 V             ; -0.0428 V          ; 0.161 V                             ; 0.071 V                             ; 4.71e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0703 V           ; 0.234 V                              ; 0.091 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0703 V          ; 0.234 V                             ; 0.091 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1842     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 245      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8471     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17978680 ; 0        ; 115760   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1404891  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 18411    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25299    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1842     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 245      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8471     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17978680 ; 0        ; 115760   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1404891  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 18411    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25299    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4820     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4820     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 21    ; 21   ;
; Unconstrained Input Port Paths  ; 21    ; 21   ;
; Unconstrained Output Ports      ; 54    ; 54   ;
; Unconstrained Output Port Paths ; 92    ; 92   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Nov 11 22:22:45 2019
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.639
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.639      -274.407 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.675        -1.675 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.298       -10.605 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.214         0.000 FPGA_CLK 
    Info (332119):     1.022         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.773         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.823
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.823      -130.025 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.824        -0.824 FPGA_CLK 
    Info (332119):     0.339         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.412         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.414         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.635         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.376
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.376       -21.384 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.325        -8.425 FPGA_CLK 
    Info (332119):     7.625         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.963         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    12.961         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.334
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.334        -8.634 FPGA_CLK 
    Info (332119):     0.337         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.480         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.256         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.680         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.600
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.600         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.720         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.535         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.374         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.259         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.595         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.530         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.269
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.269      -243.298 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.389        -1.389 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.294       -11.110 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.075         0.000 FPGA_CLK 
    Info (332119):     1.477         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.247         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.607
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.607      -113.520 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.675        -0.675 FPGA_CLK 
    Info (332119):     0.346         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.362         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.362         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.380         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.167
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.167       -19.503 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.334        -8.670 FPGA_CLK 
    Info (332119):     8.016         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.340         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.376         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.253
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.253        -6.564 FPGA_CLK 
    Info (332119):     0.302         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.343         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.014         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.277         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.596
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.596         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.733         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.533         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.370         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.282         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.643         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.896
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.896      -143.821 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.171        -7.116 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.151        -0.151 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.387         0.000 FPGA_CLK 
    Info (332119):     3.237         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.079         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.057
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.057       -77.623 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.639        -0.639 FPGA_CLK 
    Info (332119):     0.135         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    11.423         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.220
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.220       -10.980 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.177         0.000 FPGA_CLK 
    Info (332119):     9.629         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.776         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    15.109         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.363
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.363        -9.438 FPGA_CLK 
    Info (332119):     0.033         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.722         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.086         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.780         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.655
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.655         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.801         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.593         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.380         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.338         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 585 megabytes
    Info: Processing ended: Mon Nov 11 22:22:55 2019
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:13


