TimeQuest Timing Analyzer report for atari800core
Wed Sep 11 22:01:01 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 18. Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'
 19. Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 21. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 23. Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'
 24. Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'
 26. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 27. Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'
 29. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 30. Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 38. Setup Times
 39. Hold Times
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Propagation Delay
 43. Minimum Propagation Delay
 44. Output Enable Times
 45. Minimum Output Enable Times
 46. Output Disable Times
 47. Minimum Output Disable Times
 48. Slow 1200mV 85C Model Metastability Report
 49. Slow 1200mV 0C Model Fmax Summary
 50. Slow 1200mV 0C Model Setup Summary
 51. Slow 1200mV 0C Model Hold Summary
 52. Slow 1200mV 0C Model Recovery Summary
 53. Slow 1200mV 0C Model Removal Summary
 54. Slow 1200mV 0C Model Minimum Pulse Width Summary
 55. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 56. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 57. Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 58. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 60. Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'
 61. Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 63. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 65. Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'
 66. Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 67. Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'
 68. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'
 71. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 74. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 76. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 77. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
 78. Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
 80. Setup Times
 81. Hold Times
 82. Clock to Output Times
 83. Minimum Clock to Output Times
 84. Propagation Delay
 85. Minimum Propagation Delay
 86. Output Enable Times
 87. Minimum Output Enable Times
 88. Output Disable Times
 89. Minimum Output Disable Times
 90. Slow 1200mV 0C Model Metastability Report
 91. Fast 1200mV 0C Model Setup Summary
 92. Fast 1200mV 0C Model Hold Summary
 93. Fast 1200mV 0C Model Recovery Summary
 94. Fast 1200mV 0C Model Removal Summary
 95. Fast 1200mV 0C Model Minimum Pulse Width Summary
 96. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 97. Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
 98. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 99. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
100. Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
101. Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'
102. Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
104. Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'
105. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
106. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
107. Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
108. Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'
109. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
111. Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'
112. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
113. Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
116. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
117. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
118. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'
119. Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'
120. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'
121. Setup Times
122. Hold Times
123. Clock to Output Times
124. Minimum Clock to Output Times
125. Propagation Delay
126. Minimum Propagation Delay
127. Output Enable Times
128. Minimum Output Enable Times
129. Output Disable Times
130. Minimum Output Disable Times
131. Fast 1200mV 0C Model Metastability Report
132. Multicorner Timing Analysis Summary
133. Setup Times
134. Hold Times
135. Clock to Output Times
136. Minimum Clock to Output Times
137. Progagation Delay
138. Minimum Progagation Delay
139. Board Trace Model Assignments
140. Input Transition Times
141. Slow Corner Signal Integrity Metrics
142. Fast Corner Signal Integrity Metrics
143. Setup Transfers
144. Hold Transfers
145. Recovery Transfers
146. Removal Transfers
147. Report TCCS
148. Report RSKM
149. Unconstrained Paths
150. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C25E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.75        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  25.0%      ;
;     Processors 3-6         ;  12.5%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Wed Sep 11 22:00:54 2019 ;
+------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; Clock Name                                                            ; Type      ; Period    ; Frequency  ; Rise   ; Fall      ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                               ; Source                                                                  ; Targets                                                                   ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+
; CLOCK_27[0]                                                           ; Base      ; 37.037    ; 27.0 MHz   ; 0.000  ; 18.518    ;            ;           ;             ;        ;        ;           ;            ;          ;                                                                      ;                                                                         ; { CLOCK_27[0] }                                                           ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.810     ; 113.51 MHz ; 0.000  ; 4.405     ; 50.00      ; 27        ; 100         ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 17.621    ; 56.75 MHz  ; 0.000  ; 8.810     ; 50.00      ; 27        ; 50          ;        ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 8.810     ; 113.51 MHz ; -2.447 ; 1.958     ; 50.00      ; 27        ; 100         ; -100.0 ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 88105.638 ; 0.01 MHz   ; -2.447 ; 44050.372 ; 50.00      ; 2700      ; 1           ; -0.0   ;        ;           ;            ; false    ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] } ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 32.631    ; 30.65 MHz  ; 0.000  ; 16.315    ; 50.00      ; 200       ; 227         ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; Generated ; 83.333    ; 12.0 MHz   ; 0.000  ; 41.666    ; 50.00      ; 9         ; 4           ;        ;        ;           ;            ; false    ; CLOCK_27[0]                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]              ; { reconfig_pll|altpll_component|auto_generated|pll1|clk[0] }              ;
+-----------------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------------------------------------------------------------------+-------------------------------------------------------------------------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 58.8 MHz   ; 58.8 MHz        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 67.42 MHz  ; 67.42 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 135.39 MHz ; 135.39 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 145.39 MHz ; 145.39 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;                                                               ;
; 313.28 MHz ; 250.0 MHz       ; CLOCK_27[0]                                                           ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                            ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.851 ; -11.629       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547 ; -1.547        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.018 ; -0.018        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.890  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.442 ; 0.000         ;
; CLOCK_27[0]                                                           ; 33.845 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.583 ; -1.583        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.355  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.453  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.453  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.455  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.627  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                         ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -1.131 ; -10.179       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.981  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10.890 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.429 ; -3.861        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.589  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.278  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                 ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.093     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.224     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.379     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.274    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.275    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.593    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.506 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                  ; To Node                                                                                                                              ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -4.851 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                    ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                              ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -4.052     ; 0.880      ;
; -3.390 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.712     ; 0.883      ;
; -3.388 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                   ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.712     ; 0.881      ;
; 0.615  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 17.383     ;
; 0.662  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.389      ; 17.349     ;
; 0.680  ; user_io:my_user_io|Equal5~0_OTERM1                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.181     ; 0.949      ;
; 0.701  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 16.832     ;
; 0.708  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.812     ;
; 0.723  ; user_io:my_user_io|ps2_kbd_data                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.181     ; 0.906      ;
; 0.734  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 17.264     ;
; 0.764  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 17.234     ;
; 0.790  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.747     ;
; 0.797  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.727     ;
; 0.803  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.717     ;
; 0.827  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.693     ;
; 0.892  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.632     ;
; 0.893  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.647     ;
; 0.893  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.647     ;
; 0.893  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.647     ;
; 0.893  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.082     ; 16.647     ;
; 0.900  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.627     ;
; 0.900  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.627     ;
; 0.900  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.627     ;
; 0.900  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.627     ;
; 0.916  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 17.082     ;
; 0.916  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.608     ;
; 0.995  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.532     ;
; 0.995  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.532     ;
; 0.995  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.532     ;
; 0.995  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.532     ;
; 1.003  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.536     ;
; 1.009  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.511     ;
; 1.010  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.516     ;
; 1.019  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.508     ;
; 1.019  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.508     ;
; 1.019  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.508     ;
; 1.019  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.508     ;
; 1.053  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 16.485     ;
; 1.053  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.486     ;
; 1.060  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.097     ; 16.465     ;
; 1.060  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.466     ;
; 1.080  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.380      ; 16.922     ;
; 1.087  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.367      ; 16.902     ;
; 1.098  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.426     ;
; 1.105  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.421     ;
; 1.114  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.435     ;
; 1.119  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.430     ;
; 1.120  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.429     ;
; 1.120  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.429     ;
; 1.121  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.428     ;
; 1.121  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.415     ;
; 1.126  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.410     ;
; 1.127  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.409     ;
; 1.127  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.409     ;
; 1.128  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.408     ;
; 1.129  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.397     ;
; 1.151  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.073     ; 16.398     ;
; 1.155  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.097     ; 16.370     ;
; 1.155  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.371     ;
; 1.157  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.384      ; 16.849     ;
; 1.158  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.378     ;
; 1.164  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 16.829     ;
; 1.173  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.366     ;
; 1.174  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.365     ;
; 1.175  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.083     ; 16.364     ;
; 1.179  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.097     ; 16.346     ;
; 1.179  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.347     ;
; 1.180  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.346     ;
; 1.181  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.345     ;
; 1.182  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.367      ; 16.807     ;
; 1.182  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.344     ;
; 1.188  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.092     ; 16.342     ;
; 1.201  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.326     ;
; 1.201  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.326     ;
; 1.201  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.326     ;
; 1.201  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 16.326     ;
; 1.203  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.334     ;
; 1.206  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.367      ; 16.783     ;
; 1.210  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.314     ;
; 1.216  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.320     ;
; 1.219  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 16.779     ;
; 1.221  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.315     ;
; 1.222  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.314     ;
; 1.222  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.314     ;
; 1.223  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.313     ;
; 1.223  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM229                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.085     ; 16.314     ;
; 1.230  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM229                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 16.294     ;
; 1.234  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.376      ; 16.764     ;
; 1.235  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 16.308     ;
; 1.240  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.296     ;
; 1.245  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.291     ;
; 1.246  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.290     ;
; 1.246  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.290     ;
; 1.247  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.289     ;
; 1.253  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 16.283     ;
; 1.259  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.371      ; 16.734     ;
; 1.266  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.389      ; 16.745     ;
; 1.268  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 16.255     ;
; 1.273  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.102     ; 16.247     ;
; 1.275  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.096     ; 16.251     ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.547 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -2.032     ; 1.341      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.018 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.357      ; 1.587      ;
; 34.250 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.809     ; 8.999      ;
; 34.732 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.818     ; 8.508      ;
; 35.775 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.437     ; 7.846      ;
; 35.777 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.437     ; 7.844      ;
; 35.962 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.437     ; 7.659      ;
; 36.110 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.437     ; 7.511      ;
; 36.359 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.420     ; 7.279      ;
; 36.362 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.420     ; 7.276      ;
; 36.514 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.437     ; 7.107      ;
; 36.526 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.418     ; 7.114      ;
; 36.527 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.418     ; 7.113      ;
; 36.586 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.420     ; 7.052      ;
; 36.588 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.417     ; 7.053      ;
; 36.658 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.417     ; 6.983      ;
; 36.730 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.420     ; 6.908      ;
; 36.752 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.418     ; 6.888      ;
; 36.896 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.418     ; 6.744      ;
; 37.015 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.419     ; 6.624      ;
; 37.017 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.419     ; 6.622      ;
; 37.149 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.418     ; 6.491      ;
; 37.202 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.419     ; 6.437      ;
; 37.307 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.420     ; 6.331      ;
; 37.326 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 8.433      ;
; 37.350 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.419     ; 6.289      ;
; 37.520 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 8.239      ;
; 37.579 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.419     ; 6.060      ;
; 37.679 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 8.080      ;
; 37.717 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 8.042      ;
; 37.726 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 8.033      ;
; 37.995 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.428     ; 5.635      ;
; 38.062 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 7.697      ;
; 38.079 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 4.091      ; 7.680      ;
; 38.622 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.422     ; 5.014      ;
; 38.934 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.422     ; 4.702      ;
; 40.450 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.123     ; 1.094      ;
; 40.451 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.123     ; 1.093      ;
; 73.995 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 9.254      ;
; 74.174 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 9.075      ;
; 74.237 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 9.018      ;
; 74.373 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.876      ;
; 74.382 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.867      ;
; 74.383 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.866      ;
; 74.416 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.839      ;
; 74.503 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.752      ;
; 74.615 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.640      ;
; 74.624 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.631      ;
; 74.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.630      ;
; 74.682 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.573      ;
; 74.716 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.533      ;
; 74.720 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.085     ; 8.529      ;
; 74.782 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.473      ;
; 74.881 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.374      ;
; 74.890 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.365      ;
; 74.891 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.364      ;
; 74.958 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.297      ;
; 74.961 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.294      ;
; 74.962 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.293      ;
; 75.160 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.095      ;
; 75.169 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.086      ;
; 75.170 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.085      ;
; 75.224 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.031      ;
; 75.228 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 8.027      ;
; 75.503 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.752      ;
; 75.507 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.079     ; 7.748      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 77.935 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.321      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.079 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.177      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.155 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.101      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.222 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 5.034      ;
; 78.304 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.952      ;
; 78.304 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.952      ;
; 78.304 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.078     ; 4.952      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.890 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -2.032     ; 1.341      ;
; 1.424 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 7.153      ;
; 1.509 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 7.068      ;
; 1.793 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 6.806      ;
; 1.845 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 6.732      ;
; 2.003 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 6.596      ;
; 2.023 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.506      ;
; 2.094 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 6.433      ;
; 2.100 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.429      ;
; 2.106 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.432      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 6.587      ;
; 2.117 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.408      ;
; 2.125 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.404      ;
; 2.126 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.403      ;
; 2.143 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 6.385      ;
; 2.155 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.384      ;
; 2.164 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 6.414      ;
; 2.166 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 6.360      ;
; 2.198 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 6.277      ;
; 2.198 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.170     ; 6.277      ;
; 2.200 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.276      ;
; 2.200 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.169     ; 6.276      ;
; 2.216 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.380      ;
; 2.225 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 6.302      ;
; 2.237 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.343      ;
; 2.238 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.297      ;
; 2.241 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 6.337      ;
; 2.246 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.334      ;
; 2.250 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 6.276      ;
; 2.273 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.154     ; 6.254      ;
; 2.274 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 6.254      ;
; 2.287 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.247      ;
; 2.288 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.246      ;
; 2.289 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 6.288      ;
; 2.301 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.279      ;
; 2.301 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.295      ;
; 2.302 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.278      ;
; 2.314 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.266      ;
; 2.315 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.146     ; 6.220      ;
; 2.327 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 6.202      ;
; 2.336 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 6.394      ;
; 2.350 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.148     ; 6.183      ;
; 2.380 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.159      ;
; 2.381 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.085     ; 6.215      ;
; 2.404 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.121      ;
; 2.411 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.123      ;
; 2.415 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 6.125      ;
; 2.421 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 6.296      ;
; 2.430 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.095      ;
; 2.436 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 6.096      ;
; 2.440 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 6.160      ;
; 2.453 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 6.073      ;
; 2.459 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 6.071      ;
; 2.470 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.156     ; 6.055      ;
; 2.473 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.065      ;
; 2.474 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.064      ;
; 2.476 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 6.056      ;
; 2.489 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 6.045      ;
; 2.490 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 6.218      ;
; 2.496 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.043      ;
; 2.498 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 6.041      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 6.031      ;
; 2.502 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.155     ; 6.024      ;
; 2.503 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.101     ; 6.077      ;
; 2.505 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.153     ; 6.023      ;
; 2.512 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.143     ; 6.026      ;
; 2.540 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 6.038      ;
; 2.543 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.165     ; 5.937      ;
; 2.543 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.083     ; 6.055      ;
; 2.544 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 6.058      ;
; 2.550 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.981      ;
; 2.551 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.980      ;
; 2.553 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 5.921      ;
; 2.553 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.171     ; 5.921      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10]                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.566 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 6.155      ;
; 2.567 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.965      ;
; 2.572 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.142     ; 5.967      ;
; 2.580 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 5.951      ;
; 2.582 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 5.952      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                     ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.442    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -2.032     ; 1.877      ;
; 88098.760 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 6.799      ;
; 88098.761 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 6.798      ;
; 88098.861 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 6.678      ;
; 88098.862 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 6.677      ;
; 88099.045 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 6.494      ;
; 88099.046 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 6.493      ;
; 88099.475 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 6.064      ;
; 88099.599 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 5.940      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.113 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.429      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.132 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.410      ;
; 88100.256 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 5.302      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.366 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.176      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.368 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 5.174      ;
; 88100.543 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 5.015      ;
; 88100.658 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 4.881      ;
; 88100.659 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 4.880      ;
; 88100.803 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 4.736      ;
; 88101.189 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.369      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.247 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.311      ;
; 88101.347 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 4.192      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.371 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 4.187      ;
; 88101.398 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.144      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.506 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 4.036      ;
; 88101.774 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.097     ; 3.768      ;
; 88101.935 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.623      ;
; 88102.059 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 3.499      ;
; 88102.701 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.100     ; 2.838      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88102.829 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.729      ;
; 88103.008 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.551      ;
; 88103.009 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.550      ;
; 88103.018 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.541      ;
; 88103.044 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.515      ;
; 88103.045 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.514      ;
; 88103.054 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.505      ;
; 88103.116 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 2.442      ;
; 88103.209 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.350      ;
; 88103.210 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.349      ;
; 88103.219 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.340      ;
; 88103.250 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.309      ;
; 88103.251 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.308      ;
; 88103.260 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.299      ;
; 88103.535 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 2.024      ;
; 88103.772 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.081     ; 1.786      ;
; 88103.779 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.080     ; 1.780      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_27[0]'                                                                                                                                                           ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.845 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 3.114      ;
; 33.935 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 3.024      ;
; 33.990 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.969      ;
; 33.992 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.967      ;
; 34.080 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.879      ;
; 34.083 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.876      ;
; 34.135 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.824      ;
; 34.228 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.731      ;
; 34.233 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.726      ;
; 34.243 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.716      ;
; 34.280 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.679      ;
; 34.280 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.679      ;
; 34.282 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.677      ;
; 34.294 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.665      ;
; 34.378 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.581      ;
; 34.391 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.568      ;
; 34.393 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.566      ;
; 34.439 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.520      ;
; 34.523 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.436      ;
; 34.534 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.425      ;
; 34.536 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.423      ;
; 34.536 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.423      ;
; 34.536 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.423      ;
; 34.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.258      ;
; 34.816 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.143      ;
; 34.816 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.143      ;
; 34.830 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.129      ;
; 34.839 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.120      ;
; 34.840 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.119      ;
; 34.849 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.110      ;
; 34.855 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.104      ;
; 34.865 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.094      ;
; 34.865 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.094      ;
; 34.877 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.082      ;
; 34.944 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.015      ;
; 34.946 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.013      ;
; 34.950 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 2.009      ;
; 34.961 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.998      ;
; 34.991 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.968      ;
; 35.007 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.952      ;
; 35.007 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.952      ;
; 35.007 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.952      ;
; 35.015 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.944      ;
; 35.024 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.935      ;
; 35.040 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.919      ;
; 35.045 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.914      ;
; 35.050 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.909      ;
; 35.089 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.870      ;
; 35.106 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.853      ;
; 35.107 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.852      ;
; 35.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.794      ;
; 35.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.794      ;
; 35.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.758      ;
; 35.210 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.749      ;
; 35.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.733      ;
; 35.230 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.729      ;
; 35.525 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.434      ;
; 35.669 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.290      ;
; 35.721 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 1.238      ;
; 36.101 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.079     ; 0.858      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.583 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.703      ; 1.519      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.494  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.785      ;
; 0.503  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.794      ;
; 0.510  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.801      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.511  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.513  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.804      ;
; 0.514  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.805      ;
; 0.521  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.812      ;
; 0.521  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.812      ;
; 0.523  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.814      ;
; 0.528  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.819      ;
; 0.535  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.826      ;
; 0.537  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.828      ;
; 0.544  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.835      ;
; 0.552  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.843      ;
; 0.553  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.844      ;
; 0.652  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.943      ;
; 0.673  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.964      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.717  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.008      ;
; 0.723  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.014      ;
; 0.726  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.017      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.739  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.743  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.743  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.038      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.039      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.750  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.751  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.042      ;
; 0.751  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.042      ;
; 0.752  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.752  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.043      ;
; 0.754  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.045      ;
; 0.761  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.052      ;
; 0.761  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.053      ;
; 0.761  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.053      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.053      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.762  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.355 ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                                                                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.205      ; 0.793      ;
; 0.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.149      ;
; 0.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.154      ;
; 0.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.158      ;
; 0.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.160      ;
; 0.430 ; scandoubler:scandoubler1|colour_reg[4]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.471      ; 1.155      ;
; 0.432 ; scandoubler:scandoubler1|colour_reg[2]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.471      ; 1.157      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.437 ; scandoubler:scandoubler1|colour_reg[5]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.471      ; 1.162      ;
; 0.438 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.171      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.168      ;
; 0.439 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.172      ;
; 0.440 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.169      ;
; 0.442 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.171      ;
; 0.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.485      ; 1.184      ;
; 0.450 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.183      ;
; 0.453 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; paddle_mode_reg                                                                                                                                                                                           ; paddle_mode_reg                                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM227                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM227                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]_OTERM179                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]_OTERM179                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]_OTERM259                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]_OTERM259                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]_OTERM157                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]_OTERM157                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]_OTERM195                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]_OTERM195                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM211                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM211                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]_OTERM243                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]_OTERM243                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]_OTERM219                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]_OTERM219                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]_OTERM187                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]_OTERM187                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]_OTERM267                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]_OTERM267                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]_OTERM169                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]_OTERM169                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]_OTERM203                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]_OTERM203                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]_OTERM235                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]_OTERM235                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]_OTERM251                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]_OTERM251                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]_OTERM175                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]_OTERM175                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM271                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]_OTERM271                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]_OTERM191                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]_OTERM191                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]_OTERM207                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]_OTERM207                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]_OTERM223                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]_OTERM223                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]_OTERM239                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]_OTERM239                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]_OTERM255                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]_OTERM255                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM231                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM231                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]_OTERM199                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]_OTERM199                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM263                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM263                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM163                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM163                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM183                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM183                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]_OTERM215                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]_OTERM215                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM247                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM247                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]_OTERM281                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]_OTERM281                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.742 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.742 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.034      ;
; 0.747 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.747 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.039      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.751 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.751 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.047      ;
; 0.755 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.047      ;
; 0.757 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.759 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.051      ;
; 0.762 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.054      ;
; 0.763 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.055      ;
; 0.764 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.764 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.056      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.765 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.057      ;
; 0.767 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.059      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.063      ;
; 0.771 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.063      ;
; 0.772 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.064      ;
; 0.786 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.078      ;
; 0.787 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.079      ;
; 0.795 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.087      ;
; 0.817 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.109      ;
; 0.860 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 1.285      ;
; 1.014 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.306      ;
; 1.093 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.386      ;
; 1.094 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.386      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.100 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.395      ;
; 1.103 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.395      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.400      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.109 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.111 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.112 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.404      ;
; 1.116 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.408      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.409      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.409      ;
; 1.117 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.409      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.410      ;
; 1.119 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.411      ;
; 1.120 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.412      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.413      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.413      ;
; 1.121 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.413      ;
; 1.124 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.416      ;
; 1.125 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.417      ;
; 1.125 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.417      ;
; 1.126 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.418      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.419      ;
; 1.129 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.421      ;
; 1.130 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.422      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.425      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.425      ;
; 1.133 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.425      ;
; 1.134 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.426      ;
; 1.140 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.432      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.434      ;
; 1.142 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.434      ;
; 1.224 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.517      ;
; 1.225 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.517      ;
; 1.232 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.526      ;
; 1.234 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.526      ;
; 1.240 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.501 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.794      ;
; 0.502 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.795      ;
; 0.511 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.804      ;
; 0.521 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 0.813      ;
; 0.572 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.865      ;
; 0.576 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.869      ;
; 0.697 ; user_io:my_user_io|ps2_tx_byte[5]                                           ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.990      ;
; 0.698 ; user_io:my_user_io|ps2_tx_byte[2]                                           ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; user_io:my_user_io|ps2_tx_byte[1]                                           ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.991      ;
; 0.699 ; user_io:my_user_io|ps2_tx_byte[6]                                           ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.992      ;
; 0.699 ; user_io:my_user_io|ps2_tx_byte[3]                                           ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.992      ;
; 0.701 ; user_io:my_user_io|ps2_tx_byte[4]                                           ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 0.994      ;
; 0.774 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.067      ;
; 0.775 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.068      ;
; 0.788 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.081      ;
; 0.850 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.142      ;
; 0.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.143      ;
; 0.850 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.143      ;
; 0.852 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.145      ;
; 0.854 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.146      ;
; 0.854 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.147      ;
; 0.855 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.148      ;
; 0.902 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.195      ;
; 0.915 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.207      ;
; 0.925 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.217      ;
; 0.925 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.217      ;
; 1.009 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.301      ;
; 1.059 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.351      ;
; 1.070 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.362      ;
; 1.079 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.371      ;
; 1.122 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.414      ;
; 1.133 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.425      ;
; 1.213 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.505      ;
; 1.214 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.506      ;
; 1.219 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.511      ;
; 1.226 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.518      ;
; 1.268 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.561      ;
; 1.273 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.565      ;
; 1.274 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.566      ;
; 1.323 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.615      ;
; 1.382 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.674      ;
; 1.393 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.685      ;
; 1.422 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.714      ;
; 1.548 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 1.841      ;
; 1.567 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.859      ;
; 1.577 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 1.869      ;
; 1.831 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.123      ;
; 1.859 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.152      ;
; 1.865 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.158      ;
; 1.876 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.169      ;
; 1.878 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.171      ;
; 1.880 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.173      ;
; 1.883 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.176      ;
; 1.884 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.177      ;
; 1.891 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.183      ;
; 1.895 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.188      ;
; 1.908 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.201      ;
; 1.929 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.080      ; 2.221      ;
; 1.940 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.233      ;
; 1.985 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.278      ;
; 2.141 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.434      ;
; 2.150 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.443      ;
; 2.199 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.492      ;
; 2.301 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.594      ;
; 2.347 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.097      ; 2.656      ;
; 2.537 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 2.830      ;
; 2.688 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.000      ;
; 2.917 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 3.210      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.952 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.264      ;
; 2.977 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 3.270      ;
; 3.012 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 3.305      ;
; 3.117 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.429      ;
; 3.226 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; -1.746     ; 1.601      ;
; 3.357 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 3.669      ;
; 3.429 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.097      ; 3.738      ;
; 3.690 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 3.983      ;
; 3.785 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.081      ; 4.078      ;
; 3.838 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.097      ; 4.147      ;
; 4.015 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.097      ; 4.324      ;
; 4.015 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.097      ; 4.324      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
; 4.591 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.100      ; 4.903      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_27[0]'                                                                                                                                                           ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.749 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.767 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.058      ;
; 0.946 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.237      ;
; 1.088 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.379      ;
; 1.095 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.386      ;
; 1.119 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.410      ;
; 1.127 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.418      ;
; 1.128 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.419      ;
; 1.137 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.428      ;
; 1.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.523      ;
; 1.234 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.240 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.531      ;
; 1.241 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.532      ;
; 1.241 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.532      ;
; 1.256 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.547      ;
; 1.267 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.558      ;
; 1.276 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.567      ;
; 1.284 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.575      ;
; 1.304 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.595      ;
; 1.356 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.647      ;
; 1.358 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.649      ;
; 1.358 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.649      ;
; 1.362 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.653      ;
; 1.362 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.653      ;
; 1.378 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.669      ;
; 1.386 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.677      ;
; 1.387 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.678      ;
; 1.395 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.686      ;
; 1.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.693      ;
; 1.412 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.703      ;
; 1.413 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.704      ;
; 1.419 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.710      ;
; 1.420 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.711      ;
; 1.438 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.729      ;
; 1.533 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.824      ;
; 1.536 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.827      ;
; 1.536 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.827      ;
; 1.540 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.831      ;
; 1.540 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.831      ;
; 1.556 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.847      ;
; 1.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.855      ;
; 1.565 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.856      ;
; 1.565 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.856      ;
; 1.566 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.857      ;
; 1.580 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.871      ;
; 1.581 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.872      ;
; 1.706 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.997      ;
; 1.707 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 1.998      ;
; 1.709 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.000      ;
; 1.709 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.000      ;
; 1.713 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.004      ;
; 1.713 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.004      ;
; 1.797 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.088      ;
; 1.890 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.181      ;
; 1.945 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.236      ;
; 1.946 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.237      ;
; 1.948 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.239      ;
; 1.948 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.079      ; 2.239      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.627 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.747     ; 1.138      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.131 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.583      ; 4.784      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
; -1.093 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.587      ; 4.750      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.981 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.327     ; 5.361      ;
; 2.981 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 5.362      ;
; 2.981 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 5.362      ;
; 2.982 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.326     ; 5.361      ;
; 2.990 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.393     ; 5.286      ;
; 2.991 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.390     ; 5.288      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 5.484      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 5.483      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.485      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 5.486      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 5.486      ;
; 2.995 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 5.484      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 5.282      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.381     ; 5.286      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.379     ; 5.288      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.380     ; 5.287      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.380     ; 5.287      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.379     ; 5.288      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.385     ; 5.282      ;
; 3.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.381     ; 5.286      ;
; 3.003 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.386     ; 5.280      ;
; 3.003 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.386     ; 5.280      ;
; 3.013 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 5.425      ;
; 3.013 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.245     ; 5.423      ;
; 3.013 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.251     ; 5.417      ;
; 3.013 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.249     ; 5.419      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 5.468      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 5.468      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.200     ; 5.467      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 5.464      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 5.464      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.202     ; 5.465      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.466      ;
; 3.014 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.201     ; 5.466      ;
; 3.015 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.199     ; 5.467      ;
; 3.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.266     ; 5.392      ;
; 3.024 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.263     ; 5.394      ;
; 3.031 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.242     ; 5.408      ;
; 3.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.403      ;
; 3.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 5.403      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 5.388      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.258     ; 5.388      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 5.394      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.252     ; 5.394      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.253     ; 5.393      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.253     ; 5.393      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 5.392      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.254     ; 5.392      ;
; 3.035 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.248     ; 5.398      ;
; 3.036 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 5.386      ;
; 3.036 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.259     ; 5.386      ;
; 3.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 5.534      ;
; 3.074 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.203     ; 5.534      ;
; 3.216 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.214      ;
; 3.216 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.214      ;
; 3.216 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 5.213      ;
; 3.217 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.213      ;
; 3.225 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.282     ; 5.138      ;
; 3.226 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.279     ; 5.140      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 5.134      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.274     ; 5.134      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.268     ; 5.140      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.268     ; 5.140      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.269     ; 5.139      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.269     ; 5.139      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 5.138      ;
; 3.237 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.270     ; 5.138      ;
; 3.238 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.275     ; 5.132      ;
; 3.238 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.275     ; 5.132      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.071      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.071      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.071      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 5.071      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.197     ; 5.060      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
; 3.554 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 5.068      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.890 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.653      ;
; 10.895 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 6.657      ;
; 10.895 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 6.658      ;
; 10.895 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 6.658      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.098 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 6.445      ;
; 11.103 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.070     ; 6.449      ;
; 11.103 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 6.450      ;
; 11.103 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.069     ; 6.450      ;
; 11.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.187     ; 6.170      ;
; 11.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 6.171      ;
; 11.265 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.186     ; 6.171      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.178     ; 6.166      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.100     ; 6.208      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.207      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.207      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.207      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[4]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.101     ; 6.207      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.201      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.112     ; 6.196      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.198      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[1]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[2]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[3]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[4]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[5]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[6]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[7]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[8]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[9]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[10]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[11]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[12]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[13]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[14]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.314 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[15]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.106     ; 6.202      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.197      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.200      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.197      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.111     ; 6.196      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.107     ; 6.200      ;
; 11.315 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.110     ; 6.197      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.429 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.508      ; 4.410      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
; -0.336 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 4.512      ; 4.507      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.589 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 2.229      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.947 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.396      ; 2.554      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 1.995 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.585      ;
; 3.562 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.636      ; 4.410      ;
; 3.562 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.636      ; 4.410      ;
; 3.562 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.636      ; 4.410      ;
; 3.565 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.636      ; 4.413      ;
; 3.565 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.636      ; 4.413      ;
; 3.567 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.630      ; 4.409      ;
; 3.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.545      ; 4.507      ;
; 3.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.545      ; 4.507      ;
; 3.750 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.545      ; 4.507      ;
; 3.753 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.545      ; 4.510      ;
; 3.753 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.545      ; 4.510      ;
; 3.755 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.539      ; 4.506      ;
; 3.954 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.685      ; 4.851      ;
; 3.954 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.685      ; 4.851      ;
; 3.954 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.685      ; 4.851      ;
; 3.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.650      ; 4.840      ;
; 3.978 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.650      ; 4.840      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.423      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 4.408      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
; 4.002 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.413      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 4.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.699      ;
; 4.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 4.699      ;
; 4.278 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.198      ; 4.707      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.279 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 4.699      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.694      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.694      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 4.689      ;
; 4.280 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 4.694      ;
; 4.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 4.714      ;
; 4.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 4.714      ;
; 4.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 4.714      ;
; 4.282 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.201      ; 4.714      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.284 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.197      ; 4.712      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.695      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 4.698      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.695      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 4.698      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 4.698      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.695      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.695      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.182      ; 4.698      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 4.695      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.185      ; 4.701      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.180      ; 4.696      ;
; 4.285 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.185      ; 4.701      ;
; 4.488 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 4.827      ;
; 4.488 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 4.827      ;
; 4.488 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 4.827      ;
; 4.488 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.826      ;
; 4.513 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 4.795      ;
; 4.513 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.119      ; 4.795      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.115      ; 4.793      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.115      ; 4.793      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.121      ; 4.799      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.121      ; 4.799      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 4.798      ;
; 4.515 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.120      ; 4.798      ;
; 4.516 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.113      ; 4.792      ;
; 4.516 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.113      ; 4.792      ;
; 4.531 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.110      ; 4.804      ;
; 4.532 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.106      ; 4.801      ;
; 4.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 5.136      ;
; 4.722 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.183      ; 5.136      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.182      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.182      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.192      ; 5.182      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 5.181      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.188      ; 5.178      ;
; 4.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 5.179      ;
; 4.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.188      ; 5.179      ;
; 4.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.181      ;
; 4.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 5.181      ;
; 4.863 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.189      ; 5.197      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.093 ; 4.313        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.094 ; 4.314        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.097 ; 4.317        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.099 ; 4.319        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.100 ; 4.320        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.100 ; 4.320        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.205 ; 4.358        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.205 ; 4.363        ; 0.158          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.206 ; 4.359        ; 0.153          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.224 ; 4.368        ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.316 ; 4.440        ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.368 ; 4.368        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.440 ; 4.440        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.379 ; 8.780        ; 0.401          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.419 ; 8.820        ; 0.401          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[13]                ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]                                          ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                          ;
; 8.472 ; 8.692        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                          ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                                                      ;
; 8.474 ; 8.694        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                           ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                           ;
; 8.476 ; 8.696        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                          ;
; 8.480 ; 8.700        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                      ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                      ;
; 8.481 ; 8.701        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                      ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25]                                   ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                    ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                                    ;
; 8.482 ; 8.702        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.483 ; 8.703        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                       ;
; 8.484 ; 8.704        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[2]                                                        ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.485 ; 8.705        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[0]                          ;
; 8.486 ; 8.706        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                          ;
; 8.486 ; 8.706        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                          ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                  ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                  ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                         ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                         ;
; 8.487 ; 8.707        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                         ;
; 8.488 ; 8.708        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                   ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                          ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                          ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                                          ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[13]                                   ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18]                                   ;
; 8.489 ; 8.709        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                   ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                          ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[7]                                          ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                    ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                                                             ;
; 8.490 ; 8.710        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                                                             ;
; 8.492 ; 8.712        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[4]                                          ;
; 8.494 ; 8.714        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                          ;
; 8.494 ; 8.714        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[6]                                          ;
; 8.494 ; 8.714        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                                   ;
; 8.494 ; 8.714        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                   ;
; 8.494 ; 8.714        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7                      ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[12]                ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                          ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                          ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                    ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[17]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                    ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[23]                                   ;
; 8.495 ; 8.715        ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.274 ; 16.274       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.297 ; 16.297       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.330 ; 16.330       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.350 ; 16.350       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.354 ; 16.354       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.275 ; 18.463       ; 0.188          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.352 ; 18.572       ; 0.220          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.362 ; 18.362       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.366 ; 18.366       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.410 ; 18.410       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.415 ; 18.415       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.434 ; 18.434       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.438 ; 18.438       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.598 ; 18.598       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.602 ; 18.602       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.621 ; 18.621       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.626 ; 18.626       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.668 ; 18.668       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.672 ; 18.672       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.593 ; 41.623       ; 1.030          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 40.678 ; 41.708       ; 1.030          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ;
; 41.358 ; 41.578       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ;
; 41.359 ; 41.579       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                    ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ;
; 41.360 ; 41.580       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ;
; 41.361 ; 41.581       ; 0.220          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                        ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.506 ; 44052.726    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.508 ; 44052.728    ; 0.220          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.638 ; 44052.782    ; 0.144          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.719 ; 44052.907    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.720 ; 44052.908    ; 0.188          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.730 ; 44052.854    ; 0.124          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.775 ; 44052.775    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.777 ; 44052.777    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.782 ; 44052.782    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.854 ; 44052.854    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.859 ; 44052.859    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.860 ; 44052.860    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.976 ; 3.093 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.967 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -2.010 ; -2.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -2.014 ; -2.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -2.015 ; -2.128 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.960 ; -2.077 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.950 ; -2.067 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.951 ; -2.068 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.997 ; -2.110 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.999 ; -2.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -2.000 ; -2.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -2.011 ; -2.124 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.554  ; 2.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.333  ; 2.039  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.334  ; 2.040  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.249  ; 1.981  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.550  ; 2.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.534  ; 2.189  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.539  ; 2.194  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.536  ; 2.191  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.554  ; 2.209  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.322  ; 2.028  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.586  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.541  ; 2.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.522  ; 2.177  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.518  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.234  ; 1.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.355  ; 2.061  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.345  ; 2.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.344  ; 2.050  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.515  ; 2.170  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.533  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.533  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.229  ; 1.961  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.532  ; 2.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.541  ; 2.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.238  ; 1.970  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.527  ; 2.182  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.343  ; 2.049  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.332  ; 2.038  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.331  ; 2.037  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.343  ; 2.049  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.431  ; 4.823  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.202  ; 4.676  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 7.149  ; 7.914  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 9.814  ; 9.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 9.814  ; 9.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 9.554  ; 8.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 8.798  ; 8.300  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 8.906  ; 8.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 8.409  ; 7.871  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 8.365  ; 7.697  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 10.491 ; 9.578  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 9.917  ; 9.276  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 9.797  ; 9.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 9.582  ; 8.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 10.491 ; 9.578  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 10.348 ; 9.399  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 10.246 ; 9.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.777  ; 5.208  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 9.974  ; 9.306  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 8.296  ; 7.583  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 8.385  ; 7.873  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 9.974  ; 9.306  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 9.106  ; 8.505  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 9.589  ; 8.899  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 9.593  ; 8.858  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.731  ; 6.175  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.844 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.207 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.417  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.499  ; 1.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.500  ; 1.207  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.510  ; 1.217  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.417  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.718  ; 1.374  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.702  ; 1.358  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.707  ; 1.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.707  ; 1.363  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.704  ; 1.360  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.721  ; 1.377  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.488  ; 1.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.488  ; 1.195  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.746  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.397  ; 1.130  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.690  ; 1.346  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.687  ; 1.343  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.402  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.402  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.521  ; 1.228  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.511  ; 1.218  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.510  ; 1.217  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.684  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.684  ; 1.340  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.701  ; 1.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.701  ; 1.357  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.397  ; 1.130  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.700  ; 1.356  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.709  ; 1.365  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.406  ; 1.139  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.695  ; 1.351  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.509  ; 1.216  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.498  ; 1.205  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.497  ; 1.204  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.509  ; 1.216  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.554  ; 3.952  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 4.332  ; 3.809  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 6.183  ; 6.935  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 3.954  ; 3.574  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 5.603  ; 5.065  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 5.449  ; 4.879  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 4.564  ; 4.079  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 4.493  ; 4.049  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 4.174  ; 3.727  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 3.954  ; 3.574  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.352  ; 4.849  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.392  ; 4.898  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 5.352  ; 4.876  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.354  ; 4.849  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 6.001  ; 5.380  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 5.654  ; 5.076  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 5.770  ; 5.206  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 4.887  ; 4.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 4.222  ; 3.823  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 4.342  ; 3.921  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 4.222  ; 3.823  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 4.933  ; 4.448  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 5.225  ; 4.798  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 5.162  ; 4.584  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 5.147  ; 4.684  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 5.802  ; 5.249  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.630 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.989 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+-------------------------------------------------------------+
; Propagation Delay                                           ;
+------------+-------------+--------+-------+--------+--------+
; Input Port ; Output Port ; RR     ; RF    ; FR     ; FF     ;
+------------+-------------+--------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 10.023 ; 9.783 ; 10.558 ; 10.558 ;
+------------+-------------+--------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 9.246 ; 9.246 ; 9.760 ; 9.789 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.847 ; 2.847 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.854 ; 2.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.850 ; 2.850 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.869 ; 2.869 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.869 ; 2.869 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.958 ; 2.958 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.968 ; 2.968 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.958 ; 2.958 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.957 ; 2.957 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.847 ; 2.847 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.847 ; 2.847 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.865 ; 2.865 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.865 ; 2.865 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.864 ; 2.864 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.864 ; 2.864 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.873 ; 2.873 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.873 ; 2.873 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.009 ; 1.036 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.015 ; 1.042 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.012 ; 1.039 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.030 ; 1.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.030 ; 1.057 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.086 ; 1.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.096 ; 1.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.086 ; 1.113 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.085 ; 1.112 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.009 ; 1.036 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.009 ; 1.036 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.026 ; 1.053 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.026 ; 1.053 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.025 ; 1.052 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.025 ; 1.052 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.034 ; 1.061 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.034 ; 1.061 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.447     ; 2.933     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.443     ; 2.929     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.462     ; 2.948     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.543     ; 3.047     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.533     ; 3.037     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.532     ; 3.036     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.440     ; 2.926     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.458     ; 2.944     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.458     ; 2.944     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.457     ; 2.943     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.466     ; 2.952     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.085     ; 1.085     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.091     ; 1.091     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.088     ; 1.088     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.106     ; 1.106     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.106     ; 1.106     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.162     ; 1.162     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.172     ; 1.172     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.162     ; 1.162     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.161     ; 1.161     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.085     ; 1.085     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.085     ; 1.085     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.102     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.102     ; 1.102     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.101     ; 1.101     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.101     ; 1.101     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.110     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.110     ; 1.110     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                    ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                            ; Note                                                          ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
; 62.17 MHz  ; 62.17 MHz       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                               ;
; 70.95 MHz  ; 70.95 MHz       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ;                                                               ;
; 144.97 MHz ; 144.97 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                               ;
; 157.36 MHz ; 157.36 MHz      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ;                                                               ;
; 348.8 MHz  ; 250.0 MHz       ; CLOCK_27[0]                                                           ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+-----------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.213 ; -10.156       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.241 ; -1.241        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.083 ; -0.083        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.197  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.785 ; 0.000         ;
; CLOCK_27[0]                                                           ; 34.170 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -1.383 ; -1.383        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.341  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.402  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.402  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.403  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 9.341  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -1.162 ; -10.458       ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.373  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.418 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.254 ; -2.286        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.465  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.819  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.097     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.243     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.399     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.279    ; 0.000         ;
; CLOCK_27[0]                                                           ; 18.270    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.592    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.510 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                 ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                  ; To Node                                                                                                                              ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -4.213 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                    ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                              ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -3.501     ; 0.794      ;
; -2.972 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                          ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.382     ; 0.796      ;
; -2.971 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                   ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -2.382     ; 0.795      ;
; 0.787  ; user_io:my_user_io|Equal5~0_OTERM1                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.161     ; 0.863      ;
; 0.833  ; user_io:my_user_io|ps2_kbd_data                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.161     ; 0.817      ;
; 1.452  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; 3.593      ; 3.952      ;
; 1.536  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 16.456     ;
; 1.626  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.378      ; 16.375     ;
; 1.634  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.079     ; 15.910     ;
; 1.692  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 15.843     ;
; 1.695  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 16.297     ;
; 1.713  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.833     ;
; 1.719  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 16.273     ;
; 1.727  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 15.808     ;
; 1.771  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.766     ;
; 1.806  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.731     ;
; 1.813  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 16.179     ;
; 1.838  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.710     ;
; 1.838  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.710     ;
; 1.838  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.710     ;
; 1.838  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.710     ;
; 1.851  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 15.684     ;
; 1.856  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.128        ; 3.593      ; 3.867      ;
; 1.896  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.643     ;
; 1.896  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.643     ;
; 1.896  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.643     ;
; 1.896  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.643     ;
; 1.918  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.630     ;
; 1.930  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.607     ;
; 1.931  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.608     ;
; 1.931  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.608     ;
; 1.931  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.608     ;
; 1.931  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.608     ;
; 1.963  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.585     ;
; 1.969  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 15.566     ;
; 1.970  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.576     ;
; 1.976  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.563     ;
; 1.996  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.370      ; 15.997     ;
; 2.011  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.528     ;
; 2.021  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.518     ;
; 2.028  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.509     ;
; 2.047  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.373      ; 15.949     ;
; 2.047  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.508     ;
; 2.048  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.489     ;
; 2.050  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.505     ;
; 2.051  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.504     ;
; 2.051  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.504     ;
; 2.052  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.503     ;
; 2.054  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.361      ; 15.930     ;
; 2.055  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.484     ;
; 2.055  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.484     ;
; 2.055  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.484     ;
; 2.055  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.484     ;
; 2.056  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.483     ;
; 2.063  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.474     ;
; 2.071  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.477     ;
; 2.071  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.477     ;
; 2.074  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.075     ; 15.474     ;
; 2.075  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.068     ; 15.480     ;
; 2.089  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.361      ; 15.895     ;
; 2.097  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 15.895     ;
; 2.105  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.364      ; 15.882     ;
; 2.105  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.441     ;
; 2.107  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.439     ;
; 2.108  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.438     ;
; 2.109  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.437     ;
; 2.109  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.437     ;
; 2.110  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.436     ;
; 2.116  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.081     ; 15.426     ;
; 2.129  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.410     ;
; 2.129  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.410     ;
; 2.130  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM229                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.416     ;
; 2.132  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.407     ;
; 2.133  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.413     ;
; 2.135  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.404     ;
; 2.140  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.369      ; 15.852     ;
; 2.140  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.364      ; 15.847     ;
; 2.140  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.406     ;
; 2.143  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.403     ;
; 2.144  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.402     ;
; 2.144  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.402     ;
; 2.145  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.401     ;
; 2.148  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 15.387     ;
; 2.164  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.375     ;
; 2.164  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.375     ;
; 2.165  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.372     ;
; 2.167  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.372     ;
; 2.168  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.077     ; 15.378     ;
; 2.172  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.381      ; 15.832     ;
; 2.173  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.366     ;
; 2.173  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.366     ;
; 2.173  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.366     ;
; 2.173  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.366     ;
; 2.180  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 15.359     ;
; 2.187  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.087     ; 15.349     ;
; 2.187  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.350     ;
; 2.187  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.378      ; 15.814     ;
; 2.188  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM229                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.349     ;
; 2.200  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.086     ; 15.337     ;
; 2.206  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.072     ; 15.345     ;
+--------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -1.241 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -1.815     ; 1.267      ;
+--------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.083 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 1.204      ; 1.500      ;
; 34.619 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.741     ; 8.420      ;
; 35.076 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.749     ; 7.955      ;
; 35.830 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 7.536      ;
; 35.831 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 7.535      ;
; 36.005 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 7.361      ;
; 36.141 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 7.225      ;
; 36.440 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.399     ; 6.941      ;
; 36.441 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.399     ; 6.940      ;
; 36.531 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.414     ; 6.835      ;
; 36.580 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.395     ; 6.805      ;
; 36.601 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.397     ; 6.782      ;
; 36.604 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.397     ; 6.779      ;
; 36.645 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.396     ; 6.739      ;
; 36.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.399     ; 6.727      ;
; 36.789 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.399     ; 6.592      ;
; 36.816 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.397     ; 6.567      ;
; 36.949 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.397     ; 6.434      ;
; 37.010 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.398     ; 6.372      ;
; 37.012 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.398     ; 6.370      ;
; 37.169 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.397     ; 6.214      ;
; 37.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.398     ; 6.196      ;
; 37.310 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.399     ; 6.071      ;
; 37.322 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.398     ; 6.060      ;
; 37.541 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.398     ; 5.841      ;
; 37.611 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 7.665      ;
; 37.778 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 7.498      ;
; 37.942 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 7.334      ;
; 37.983 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 7.293      ;
; 37.985 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 7.291      ;
; 38.018 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.406     ; 5.356      ;
; 38.294 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 6.982      ;
; 38.318 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 3.607      ; 6.958      ;
; 38.622 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.757      ;
; 38.931 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.401     ; 4.448      ;
; 40.538 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.125     ; 1.005      ;
; 40.539 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.125     ; 1.004      ;
; 74.711 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.548      ;
; 74.866 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.393      ;
; 74.936 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 8.328      ;
; 75.038 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.221      ;
; 75.046 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.213      ;
; 75.050 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 8.209      ;
; 75.091 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 8.173      ;
; 75.212 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 8.052      ;
; 75.263 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 8.001      ;
; 75.271 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.993      ;
; 75.275 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.989      ;
; 75.353 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.906      ;
; 75.364 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.076     ; 7.895      ;
; 75.367 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.897      ;
; 75.470 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.794      ;
; 75.539 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.725      ;
; 75.547 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.717      ;
; 75.551 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.713      ;
; 75.578 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.686      ;
; 75.589 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.675      ;
; 75.625 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.639      ;
; 75.797 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.467      ;
; 75.805 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.459      ;
; 75.809 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.455      ;
; 75.854 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.410      ;
; 75.865 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.399      ;
; 76.112 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.152      ;
; 76.123 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 7.141      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.338 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.926      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.462 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.802      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.714      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.585 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.679      ;
; 78.668 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.596      ;
; 78.668 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.596      ;
; 78.668 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.071     ; 4.596      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.197 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -1.814     ; 1.267      ;
; 1.912 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 6.680      ;
; 2.014 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 6.578      ;
; 2.263 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 6.329      ;
; 2.282 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 6.331      ;
; 2.485 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 6.128      ;
; 2.497 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 6.003      ;
; 2.497 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.150     ; 6.003      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 6.000      ;
; 2.499 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.151     ; 6.000      ;
; 2.527 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.022      ;
; 2.528 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 6.021      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.533 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 6.182      ;
; 2.542 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 6.052      ;
; 2.546 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 6.010      ;
; 2.550 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.999      ;
; 2.555 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 5.993      ;
; 2.571 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.975      ;
; 2.583 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 6.009      ;
; 2.584 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 6.024      ;
; 2.595 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.962      ;
; 2.604 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.945      ;
; 2.619 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.930      ;
; 2.620 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.927      ;
; 2.628 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.072     ; 6.112      ;
; 2.639 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.915      ;
; 2.640 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.914      ;
; 2.652 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 5.940      ;
; 2.669 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 5.939      ;
; 2.673 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 5.875      ;
; 2.683 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.864      ;
; 2.686 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 5.922      ;
; 2.692 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.863      ;
; 2.702 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 5.892      ;
; 2.703 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 5.891      ;
; 2.721 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 5.871      ;
; 2.722 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.827      ;
; 2.726 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 5.868      ;
; 2.732 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 5.816      ;
; 2.736 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.813      ;
; 2.759 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.795      ;
; 2.765 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 5.954      ;
; 2.790 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 5.823      ;
; 2.794 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 5.761      ;
; 2.795 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 5.799      ;
; 2.805 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.149     ; 5.696      ;
; 2.812 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.742      ;
; 2.814 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 5.916      ;
; 2.821 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.094     ; 5.771      ;
; 2.823 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 5.735      ;
; 2.829 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.669      ;
; 2.829 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.152     ; 5.669      ;
; 2.838 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.708      ;
; 2.848 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.698      ;
; 2.848 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.706      ;
; 2.861 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.695      ;
; 2.862 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[11]                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 5.694      ;
; 2.872 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.687      ;
; 2.873 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 5.681      ;
; 2.887 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.660      ;
; 2.889 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.134     ; 5.663      ;
; 2.905 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.226     ; 5.555      ;
; 2.907 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 5.823      ;
; 2.911 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.092     ; 5.683      ;
; 2.915 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 5.642      ;
; 2.916 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 5.634      ;
; 2.917 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[9]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 5.633      ;
; 2.920 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 5.627      ;
; 2.922 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 5.627      ;
; 2.945 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.140     ; 5.601      ;
; 2.949 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 5.659      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.764      ;
; 2.951 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 5.659      ;
; 2.954 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 5.605      ;
; 2.962 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.753      ;
; 2.962 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.753      ;
; 2.962 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.753      ;
; 2.962 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 5.753      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.785    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -1.814     ; 1.767      ;
; 88099.283 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 6.267      ;
; 88099.283 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 6.267      ;
; 88099.293 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 6.275      ;
; 88099.293 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 6.275      ;
; 88099.456 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 6.094      ;
; 88099.456 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 6.094      ;
; 88099.801 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 5.749      ;
; 88099.910 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 5.640      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.445 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.109      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.471 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 5.083      ;
; 88100.479 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 5.089      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.644 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.910      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.667 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 4.887      ;
; 88100.778 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.790      ;
; 88100.977 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 4.573      ;
; 88100.977 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 4.573      ;
; 88101.144 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 4.406      ;
; 88101.397 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.171      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.491 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 4.077      ;
; 88101.577 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 3.973      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.600 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.968      ;
; 88101.648 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.906      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.715 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.839      ;
; 88101.989 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.086     ; 3.565      ;
; 88102.150 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.418      ;
; 88102.259 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 3.309      ;
; 88102.853 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.090     ; 2.697      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.045 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.523      ;
; 88103.251 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.317      ;
; 88103.251 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.317      ;
; 88103.261 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.307      ;
; 88103.290 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.278      ;
; 88103.290 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.278      ;
; 88103.300 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.268      ;
; 88103.313 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.255      ;
; 88103.433 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.135      ;
; 88103.433 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.135      ;
; 88103.434 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.134      ;
; 88103.434 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.134      ;
; 88103.443 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.125      ;
; 88103.449 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 2.119      ;
; 88103.748 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 1.820      ;
; 88103.946 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 1.622      ;
; 88103.958 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.072     ; 1.610      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 34.170 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.798      ;
; 34.207 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.761      ;
; 34.290 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.678      ;
; 34.297 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.671      ;
; 34.332 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.636      ;
; 34.334 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.634      ;
; 34.445 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.523      ;
; 34.459 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.509      ;
; 34.471 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.497      ;
; 34.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.461      ;
; 34.541 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.427      ;
; 34.542 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.426      ;
; 34.571 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.397      ;
; 34.582 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.386      ;
; 34.598 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.370      ;
; 34.602 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.366      ;
; 34.632 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.336      ;
; 34.669 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.299      ;
; 34.669 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.299      ;
; 34.669 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.299      ;
; 34.679 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.289      ;
; 34.758 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.210      ;
; 34.767 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.201      ;
; 34.925 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.043      ;
; 34.925 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.043      ;
; 34.946 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 2.022      ;
; 35.048 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.920      ;
; 35.057 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.911      ;
; 35.058 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.910      ;
; 35.067 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.901      ;
; 35.072 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.896      ;
; 35.081 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.887      ;
; 35.082 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.886      ;
; 35.105 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.863      ;
; 35.105 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.863      ;
; 35.105 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.863      ;
; 35.111 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.857      ;
; 35.124 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.844      ;
; 35.126 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.842      ;
; 35.151 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.817      ;
; 35.163 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.805      ;
; 35.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.770      ;
; 35.213 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.755      ;
; 35.223 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.745      ;
; 35.237 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.731      ;
; 35.239 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.729      ;
; 35.247 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.721      ;
; 35.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.716      ;
; 35.252 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.716      ;
; 35.276 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.692      ;
; 35.277 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.691      ;
; 35.288 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.680      ;
; 35.384 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.584      ;
; 35.394 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.574      ;
; 35.404 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.564      ;
; 35.408 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.560      ;
; 35.641 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.327      ;
; 35.806 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.162      ;
; 35.851 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 1.117      ;
; 36.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.071     ; 0.770      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 2.376      ; 1.375      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.456  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.721      ;
; 0.470  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.736      ;
; 0.471  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.737      ;
; 0.479  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.480  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.480  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.482  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.748      ;
; 0.486  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.752      ;
; 0.488  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.754      ;
; 0.489  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.755      ;
; 0.493  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.759      ;
; 0.498  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.764      ;
; 0.501  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.767      ;
; 0.509  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.775      ;
; 0.520  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.786      ;
; 0.523  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.789      ;
; 0.608  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.874      ;
; 0.625  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.891      ;
; 0.626  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.892      ;
; 0.638  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.904      ;
; 0.646  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.912      ;
; 0.648  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
; 0.673  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.939      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.684  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.687  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.690  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.692  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.960      ;
; 0.693  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.694  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.960      ;
; 0.695  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.961      ;
; 0.696  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.963      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.965      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.963      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.698  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.699  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.964      ;
; 0.699  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.965      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.700  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.966      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.968      ;
; 0.701  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.967      ;
; 0.702  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.967      ;
; 0.702  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.968      ;
; 0.706  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.972      ;
; 0.706  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.973      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.708  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.974      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                              ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.341 ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                                                                       ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 0.735      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.050      ;
; 0.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.053      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.058      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.059      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[0]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[5]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[5]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[0]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[1]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[2]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[2]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|keyboard_overrun_reg                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|keyboard_overrun_reg                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_overrun_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_overrun_reg                                                                                                                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[0]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_ip_framing_reg                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_ip_framing_reg                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; paddle_mode_reg                                                                                                                                                        ; paddle_mode_reg                                                                                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[9]                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.469 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.735      ;
; 0.687 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.696 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.963      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.697 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.964      ;
; 0.699 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.966      ;
; 0.700 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.967      ;
; 0.703 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.969      ;
; 0.704 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.970      ;
; 0.705 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.971      ;
; 0.706 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.972      ;
; 0.707 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.974      ;
; 0.707 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.973      ;
; 0.709 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.977      ;
; 0.710 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.711 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.977      ;
; 0.712 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.978      ;
; 0.713 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.714 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.981      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.715 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.718 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.984      ;
; 0.719 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.985      ;
; 0.731 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.997      ;
; 0.735 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.001      ;
; 0.743 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.009      ;
; 0.758 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 1.142      ;
; 0.761 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.027      ;
; 0.911 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.177      ;
; 1.006 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.010 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.011 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.277      ;
; 1.012 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.279      ;
; 1.015 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.282      ;
; 1.016 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.283      ;
; 1.018 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.285      ;
; 1.019 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.286      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.020 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.021 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.288      ;
; 1.022 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.288      ;
; 1.024 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.024 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.292      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.293      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.293      ;
; 1.027 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.294      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.294      ;
; 1.028 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.294      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.296      ;
; 1.029 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.295      ;
; 1.030 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.297      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.298      ;
; 1.032 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.298      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.299      ;
; 1.033 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.300      ;
; 1.034 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.301      ;
; 1.037 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.303      ;
; 1.038 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.304      ;
; 1.038 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.304      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.042 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.308      ;
; 1.043 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.309      ;
; 1.044 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.310      ;
; 1.045 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.311      ;
; 1.053 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.319      ;
; 1.053 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.319      ;
; 1.055 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.321      ;
; 1.107 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.373      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.108 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.116 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.383      ;
; 1.118 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.385      ;
; 1.122 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.389      ;
; 1.122 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.388      ;
; 1.127 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.393      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.463 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.730      ;
; 0.464 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.731      ;
; 0.465 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.732      ;
; 0.472 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.739      ;
; 0.488 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.755      ;
; 0.539 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.806      ;
; 0.543 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.810      ;
; 0.644 ; user_io:my_user_io|ps2_tx_byte[5]                                           ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.911      ;
; 0.645 ; user_io:my_user_io|ps2_tx_byte[6]                                           ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; user_io:my_user_io|ps2_tx_byte[1]                                           ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.912      ;
; 0.646 ; user_io:my_user_io|ps2_tx_byte[4]                                           ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; user_io:my_user_io|ps2_tx_byte[2]                                           ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.913      ;
; 0.647 ; user_io:my_user_io|ps2_tx_byte[3]                                           ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.914      ;
; 0.721 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.988      ;
; 0.722 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.989      ;
; 0.731 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 0.998      ;
; 0.792 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.059      ;
; 0.799 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.066      ;
; 0.800 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.067      ;
; 0.805 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.072      ;
; 0.805 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.072      ;
; 0.806 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.073      ;
; 0.807 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.074      ;
; 0.834 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.101      ;
; 0.840 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.107      ;
; 0.859 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.126      ;
; 0.859 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.126      ;
; 0.907 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.174      ;
; 0.970 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.237      ;
; 0.982 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.249      ;
; 0.993 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.260      ;
; 1.007 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.274      ;
; 1.050 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.317      ;
; 1.121 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.388      ;
; 1.129 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.396      ;
; 1.130 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.397      ;
; 1.149 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.416      ;
; 1.175 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.442      ;
; 1.195 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.462      ;
; 1.196 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.463      ;
; 1.238 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.505      ;
; 1.262 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.529      ;
; 1.283 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.550      ;
; 1.325 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.592      ;
; 1.430 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.697      ;
; 1.440 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.707      ;
; 1.451 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.718      ;
; 1.642 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.909      ;
; 1.653 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.920      ;
; 1.660 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.927      ;
; 1.661 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.928      ;
; 1.698 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.965      ;
; 1.700 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 1.967      ;
; 1.734 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.001      ;
; 1.735 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.002      ;
; 1.746 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.013      ;
; 1.747 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.014      ;
; 1.766 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.033      ;
; 1.780 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.047      ;
; 1.790 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.057      ;
; 1.795 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.062      ;
; 1.896 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.163      ;
; 1.902 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.169      ;
; 1.949 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.216      ;
; 2.114 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.086      ; 2.395      ;
; 2.124 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.391      ;
; 2.256 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.523      ;
; 2.395 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.680      ;
; 2.643 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.910      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.647 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 2.932      ;
; 2.654 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.921      ;
; 2.718 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 2.985      ;
; 2.802 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 3.087      ;
; 2.905 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; -1.565     ; 1.452      ;
; 3.019 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 3.304      ;
; 3.143 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.086      ; 3.424      ;
; 3.338 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 3.605      ;
; 3.413 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.072      ; 3.680      ;
; 3.562 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.086      ; 3.843      ;
; 3.711 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.086      ; 3.992      ;
; 3.711 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.086      ; 3.992      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
; 4.167 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.090      ; 4.452      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.698 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.713 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.855 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.121      ;
; 1.027 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.293      ;
; 1.030 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.030 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.296      ;
; 1.033 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.299      ;
; 1.034 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.300      ;
; 1.047 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.313      ;
; 1.152 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.418      ;
; 1.159 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.425      ;
; 1.160 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.426      ;
; 1.165 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.431      ;
; 1.166 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.432      ;
; 1.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.434      ;
; 1.169 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.435      ;
; 1.180 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.446      ;
; 1.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.464      ;
; 1.200 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.466      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.467      ;
; 1.201 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.467      ;
; 1.205 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.471      ;
; 1.205 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.471      ;
; 1.217 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.483      ;
; 1.249 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.515      ;
; 1.292 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.558      ;
; 1.298 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.564      ;
; 1.302 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.568      ;
; 1.313 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.579      ;
; 1.327 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.593      ;
; 1.328 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.594      ;
; 1.333 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.599      ;
; 1.334 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.600      ;
; 1.340 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.606      ;
; 1.362 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.628      ;
; 1.364 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.630      ;
; 1.365 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.631      ;
; 1.369 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.635      ;
; 1.369 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.635      ;
; 1.459 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.725      ;
; 1.465 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.731      ;
; 1.466 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.732      ;
; 1.469 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.735      ;
; 1.470 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.736      ;
; 1.480 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.746      ;
; 1.481 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.747      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.779      ;
; 1.513 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.779      ;
; 1.515 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.781      ;
; 1.516 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.782      ;
; 1.520 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.786      ;
; 1.520 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.786      ;
; 1.662 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.928      ;
; 1.715 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.981      ;
; 1.731 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.997      ;
; 1.731 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.997      ;
; 1.733 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 1.999      ;
; 1.734 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.071      ; 2.000      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 9.341 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -1.565     ; 1.025      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.162 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.129      ; 4.362      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
; -1.128 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 3.132      ; 4.331      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.296     ; 5.006      ;
; 3.373 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.296     ; 5.006      ;
; 3.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.296     ; 5.005      ;
; 3.374 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.296     ; 5.005      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.117      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.117      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 5.118      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 5.119      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 5.119      ;
; 3.390 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.117      ;
; 3.399 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.357     ; 4.919      ;
; 3.402 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.353     ; 4.920      ;
; 3.410 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 5.100      ;
; 3.410 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 5.100      ;
; 3.410 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 5.096      ;
; 3.410 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 5.099      ;
; 3.410 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.177     ; 5.099      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.344     ; 4.920      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.342     ; 4.922      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 4.914      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.350     ; 4.914      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 4.921      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.343     ; 4.921      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.342     ; 4.922      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.344     ; 4.920      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 5.099      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.176     ; 5.099      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.180     ; 5.095      ;
; 3.411 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.179     ; 5.096      ;
; 3.412 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.348     ; 4.915      ;
; 3.412 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.348     ; 4.915      ;
; 3.430 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.214     ; 5.042      ;
; 3.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.216     ; 5.039      ;
; 3.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.033      ;
; 3.431 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.221     ; 5.034      ;
; 3.436 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 5.013      ;
; 3.439 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.233     ; 5.014      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 5.008      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.230     ; 5.008      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.016      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.016      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.015      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.223     ; 5.015      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 5.014      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.224     ; 5.014      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.222     ; 5.016      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 5.021      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.217     ; 5.021      ;
; 3.448 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.215     ; 5.023      ;
; 3.449 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.228     ; 5.009      ;
; 3.449 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.228     ; 5.009      ;
; 3.474 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 5.160      ;
; 3.474 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 5.160      ;
; 3.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 4.864      ;
; 3.597 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 4.864      ;
; 3.598 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 4.863      ;
; 3.598 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 4.863      ;
; 3.623 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.250     ; 4.777      ;
; 3.626 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.246     ; 4.778      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.772      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.243     ; 4.772      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 4.780      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.235     ; 4.780      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 4.779      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.236     ; 4.779      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 4.778      ;
; 3.635 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.237     ; 4.778      ;
; 3.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 4.773      ;
; 3.636 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.241     ; 4.773      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.702      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.702      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.178     ; 4.702      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.172     ; 4.708      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.167     ; 4.713      ;
; 3.932 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.164     ; 4.716      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.418 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.134      ;
; 11.420 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 6.139      ;
; 11.420 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 6.140      ;
; 11.420 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 6.140      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.549 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.071     ; 6.003      ;
; 11.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.064     ; 6.008      ;
; 11.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 6.009      ;
; 11.551 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.063     ; 6.009      ;
; 11.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.165     ; 5.717      ;
; 11.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 5.718      ;
; 11.741 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.164     ; 5.718      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.755 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.156     ; 5.712      ;
; 11.820 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 5.714      ;
; 11.820 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 5.714      ;
; 11.820 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 5.714      ;
; 11.820 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[4]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 5.714      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.088     ; 5.714      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.093     ; 5.709      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.095     ; 5.707      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.703      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.704      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[1]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[2]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[3]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[4]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[5]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[6]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[7]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[8]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[9]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[10]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[11]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[12]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[13]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[14]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.821 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[15]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.094     ; 5.708      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.703      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.703      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.703      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.098     ; 5.703      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
; 11.822 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.099     ; 5.702      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.254 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.935      ; 3.995      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
; -0.147 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 3.938      ; 4.105      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.465 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.379      ; 2.034      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.311      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.331      ; 2.327      ;
; 3.217 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.585      ; 3.997      ;
; 3.217 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.585      ; 3.997      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.995      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.995      ;
; 3.219 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 3.995      ;
; 3.225 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.574      ; 3.994      ;
; 3.406 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.506      ; 4.107      ;
; 3.406 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.506      ; 4.107      ;
; 3.408 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.105      ;
; 3.408 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.105      ;
; 3.408 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.502      ; 4.105      ;
; 3.414 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.495      ; 4.104      ;
; 3.550 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 4.382      ;
; 3.550 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 4.382      ;
; 3.550 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 4.382      ;
; 3.575 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.601      ; 4.371      ;
; 3.576 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.600      ; 4.371      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.006      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.167      ; 3.991      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.168      ; 3.992      ;
; 3.629 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.168      ; 3.992      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 3.819 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 4.208      ;
; 3.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.195      ;
; 3.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.195      ;
; 3.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.195      ;
; 3.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.201      ;
; 3.820 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.191      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.821 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 4.201      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.824 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 4.210      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.194      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.197      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.194      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.197      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.213      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.197      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.194      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.213      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.213      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.194      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 4.213      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 4.197      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 4.194      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.200      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 4.195      ;
; 3.825 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 4.200      ;
; 4.016 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.318      ;
; 4.016 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 4.318      ;
; 4.016 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 4.317      ;
; 4.017 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 4.318      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 4.276      ;
; 4.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 4.276      ;
; 4.031 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 4.283      ;
; 4.031 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.104      ; 4.283      ;
; 4.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.106      ; 4.286      ;
; 4.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.106      ; 4.286      ;
; 4.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.105      ; 4.285      ;
; 4.032 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.105      ; 4.285      ;
; 4.033 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.099      ; 4.280      ;
; 4.033 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.099      ; 4.280      ;
; 4.042 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.095      ; 4.285      ;
; 4.046 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 4.285      ;
; 4.210 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 4.584      ;
; 4.210 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 4.584      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 4.650      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 4.650      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.649      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.646      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.646      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 4.646      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.649      ;
; 4.351 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.649      ;
; 4.352 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 4.650      ;
; 4.365 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.112      ; 4.608      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.097 ; 4.313        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.098 ; 4.314        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.099 ; 4.315        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.102 ; 4.318        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.103 ; 4.319        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ;
; 4.206 ; 4.356        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ;
; 4.207 ; 4.357        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ;
; 4.208 ; 4.358        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ;
; 4.209 ; 4.359        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ;
; 4.211 ; 4.361        ; 0.150          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.243 ; 4.369        ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.330 ; 4.439        ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.369 ; 4.369        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.439 ; 4.439        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                    ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.399 ; 8.781        ; 0.382          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 8.444 ; 8.826        ; 0.382          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[0]                                          ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[1]                                          ;
; 8.447 ; 8.663        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[2]                                          ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[13]                ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[2]                                                        ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25]                                   ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                    ;
; 8.448 ; 8.664        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                                    ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[0]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[7]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[7]                                          ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[13]                                   ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18]                                   ;
; 8.450 ; 8.666        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                   ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                    ;
; 8.453 ; 8.669        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_control_reg[2]                                                     ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                  ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                          ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                         ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                         ;
; 8.455 ; 8.671        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                         ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                          ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[17]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                    ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[23]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                   ;
; 8.456 ; 8.672        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                           ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[12]                ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                          ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[5]                                          ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[6]                                          ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                    ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[4]                                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[5]                                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                       ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                   ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                                                      ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                        ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                           ;
; 8.457 ; 8.673        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[4]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]~_Duplicate_4                             ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                          ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                                   ;
; 8.458 ; 8.674        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]                                   ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.279 ; 16.279       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.283 ; 16.283       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.294 ; 16.294       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.334 ; 16.334       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.348 ; 16.348       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.351 ; 16.351       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.270 ; 18.454       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.344 ; 18.344       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.351 ; 18.351       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.364 ; 18.580       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 18.400 ; 18.400       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.403 ; 18.403       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.423 ; 18.423       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.430 ; 18.430       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.606 ; 18.606       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 18.613 ; 18.613       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 18.633 ; 18.633       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 18.634 ; 18.634       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 18.637 ; 18.637       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 18.684 ; 18.684       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 18.691 ; 18.691       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 34.550 ; 37.037       ; 2.487          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.592 ; 41.602       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 40.718 ; 41.728       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                               ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ;
; 41.361 ; 41.577       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_ena_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_ena_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_ena_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_ena_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_counter_state                                                        ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|tmp_seq_ena_state                                                             ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                        ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ;
; 41.362 ; 41.578       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                   ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                    ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3] ;
; 41.363 ; 41.579       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.510 ; 44052.726    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.513 ; 44052.729    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.657 ; 44052.783    ; 0.126          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.720 ; 44052.904    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.723 ; 44052.907    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.744 ; 44052.853    ; 0.109          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.780 ; 44052.780    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.783 ; 44052.783    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.853 ; 44052.853    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.856 ; 44052.856    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.151 ; 88105.638    ; 2.487          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.632 ; 2.745 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.636 ; 2.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.637 ; 2.750 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.591 ; 2.708 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.581 ; 2.698 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.619 ; 2.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.619 ; 2.732 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.621 ; 2.734 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.621 ; 2.734 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.622 ; 2.735 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.633 ; 2.746 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -1.686 ; -1.804 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -1.739 ; -1.853 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -1.743 ; -1.857 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -1.745 ; -1.859 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -1.745 ; -1.859 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -1.686 ; -1.804 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -1.696 ; -1.814 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -1.687 ; -1.805 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -1.687 ; -1.805 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -1.726 ; -1.840 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -1.728 ; -1.842 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -1.728 ; -1.842 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -1.729 ; -1.843 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -1.729 ; -1.843 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -1.740 ; -1.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -1.740 ; -1.854 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.449  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.516  ; 2.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.786  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.723  ; 2.385  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.719  ; 2.381  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.549  ; 2.262  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.430  ; 2.169  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.733  ; 2.395  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.439  ; 2.178  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.600  ; 4.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.363  ; 4.789  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 6.954  ; 8.043  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 9.703  ; 8.670  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 9.703  ; 8.670  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 9.420  ; 8.394  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 8.553  ; 7.892  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 8.887  ; 7.770  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 8.195  ; 7.487  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 8.344  ; 7.353  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 10.398 ; 9.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 9.765  ; 8.782  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 9.726  ; 8.536  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 9.457  ; 8.489  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 10.398 ; 9.051  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 10.289 ; 8.872  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 10.161 ; 8.867  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.948  ; 5.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 9.705  ; 8.772  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 8.311  ; 7.237  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 8.326  ; 7.493  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 9.705  ; 8.772  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 8.886  ; 8.060  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 9.383  ; 8.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 9.571  ; 8.377  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.855  ; 6.098  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.558 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.945 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.800  ; 1.514  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.801  ; 1.515  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.724  ; 1.464  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.025  ; 1.688  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.009  ; 1.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.014  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.010  ; 1.673  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.026  ; 1.689  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.789  ; 1.503  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.789  ; 1.503  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.054  ; 1.787  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.998  ; 1.661  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.994  ; 1.657  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.710  ; 1.450  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.822  ; 1.536  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.812  ; 1.526  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.991  ; 1.654  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.009  ; 1.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.009  ; 1.672  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.705  ; 1.445  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.008  ; 1.671  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.017  ; 1.680  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.714  ; 1.454  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.999  ; 1.662  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.799  ; 1.513  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.798  ; 1.512  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.811  ; 1.525  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 4.832  ; 4.137  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 4.603  ; 4.034  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 6.112  ; 7.176  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 4.090  ; 3.649  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 5.686  ; 4.992  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 5.534  ; 4.804  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 4.684  ; 4.102  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 4.627  ; 4.067  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 4.276  ; 3.787  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 4.090  ; 3.649  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 5.438  ; 4.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 5.485  ; 4.864  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 5.438  ; 4.820  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 5.439  ; 4.808  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 6.068  ; 5.276  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 5.758  ; 4.976  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 5.844  ; 5.108  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.166  ; 4.466  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 4.368  ; 3.879  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 4.462  ; 3.958  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 4.368  ; 3.879  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 5.048  ; 4.435  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 5.307  ; 4.740  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 5.306  ; 4.534  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 5.277  ; 4.644  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.036  ; 5.291  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.243 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.626 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.993 ; 8.922 ; 9.463 ; 9.463 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 8.587 ; 8.451 ; 8.903 ; 8.903 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.527 ; 2.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.534 ; 2.534 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.530 ; 2.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.548 ; 2.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.548 ; 2.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.635 ; 2.635 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.645 ; 2.645 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.634 ; 2.634 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.634 ; 2.634 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.527 ; 2.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.527 ; 2.527 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.545 ; 2.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.545 ; 2.545 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.544 ; 2.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.544 ; 2.544 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.553 ; 2.553 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.280 ; 1.314 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.287 ; 1.321 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.283 ; 1.317 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.302 ; 1.336 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.302 ; 1.336 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.363 ; 1.396 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.353 ; 1.386 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.280 ; 1.314 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.280 ; 1.314 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.298 ; 1.332 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.298 ; 1.332 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.297 ; 1.331 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.297 ; 1.331 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.306 ; 1.340 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.206     ; 2.603     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.213     ; 2.610     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.209     ; 2.606     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.227     ; 2.624     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.227     ; 2.624     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.290     ; 2.711     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.300     ; 2.721     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.289     ; 2.710     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.289     ; 2.710     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.206     ; 2.603     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.206     ; 2.603     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.224     ; 2.621     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.224     ; 2.621     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.223     ; 2.620     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.223     ; 2.620     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.232     ; 2.629     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.360     ; 1.360     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.356     ; 1.356     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.375     ; 1.375     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.436     ; 1.436     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.426     ; 1.426     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.353     ; 1.353     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.371     ; 1.371     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.371     ; 1.371     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.370     ; 1.370     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.379     ; 1.379     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                             ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -2.319 ; -5.288        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 0.181  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0.392  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.829  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 13.668 ; 0.000         ;
; CLOCK_27[0]                                                           ; 35.614 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                              ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.996 ; -0.996        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.111  ; 0.000         ;
; CLOCK_27[0]                                                           ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.186  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 8.109  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                          ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.357 ; -3.213        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.058  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 14.588 ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                           ;
+-----------------------------------------------------------------------+--------+---------------+
; Clock                                                                 ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------+--------+---------------+
; CLOCK_27[0]                                                           ; -0.378 ; -3.402        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.686  ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.919  ; 0.000         ;
+-----------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                  ;
+-----------------------------------------------------------------------+-----------+---------------+
; Clock                                                                 ; Slack     ; End Point TNS ;
+-----------------------------------------------------------------------+-----------+---------------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.186     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 4.331     ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.560     ; 0.000         ;
; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 16.300    ; 0.000         ;
; CLOCK_27[0]                                                           ; 17.785    ; 0.000         ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 40.634    ; 0.000         ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 44052.600 ; 0.000         ;
+-----------------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                  ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; -2.319 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                    ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                               ; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.150        ; -2.015     ; 0.371      ;
; -1.486 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.303     ; 0.374      ;
; -1.483 ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                   ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.354        ; -1.303     ; 0.371      ;
; 1.318  ; user_io:my_user_io|Equal5~0_OTERM1                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.085     ; 0.393      ;
; 1.329  ; user_io:my_user_io|ps2_kbd_data                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_dat|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; -0.085     ; 0.382      ;
; 1.662  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.809        ; 1.957      ; 2.091      ;
; 1.938  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                                      ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|synchronizer:sync_clk|ff_reg[2]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.128        ; 1.957      ; 2.134      ;
; 6.998  ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[5]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 1.709      ;
; 7.234  ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:1:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.810        ; -0.961     ; 0.543      ;
; 7.374  ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[3]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.073     ; 1.351      ;
; 7.476  ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[2]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.073     ; 1.249      ;
; 7.504  ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[0]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.073     ; 1.221      ;
; 7.506  ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[4]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.074     ; 1.218      ;
; 7.533  ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[7]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.078     ; 1.187      ;
; 7.562  ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[6]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.073     ; 1.163      ;
; 7.586  ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[1]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.078     ; 1.134      ;
; 7.621  ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[25]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.089     ; 1.088      ;
; 7.697  ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[15]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.084     ; 1.017      ;
; 7.743  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                                        ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.089     ; 0.966      ;
; 7.805  ; sdram_statemachine:sdram_adaptor|reply_reg                                                                 ; sdram_statemachine:sdram_adaptor|reply_sreg                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.902      ;
; 7.892  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                                                        ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.089     ; 0.817      ;
; 7.936  ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[10]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.780      ;
; 7.955  ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[13]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.761      ;
; 7.996  ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[11]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.720      ;
; 8.074  ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[9]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.083     ; 0.641      ;
; 8.115  ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                        ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.591      ;
; 8.135  ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[12]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.082     ; 0.581      ;
; 8.162  ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.544      ;
; 8.163  ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.544      ;
; 8.165  ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[22]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.541      ;
; 8.166  ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.540      ;
; 8.170  ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[29]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.542      ;
; 8.172  ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[28]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.086     ; 0.540      ;
; 8.266  ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[17]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.441      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.438      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.438      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.445      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[26]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.438      ;
; 8.268  ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[16]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.438      ;
; 8.269  ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.438      ;
; 8.269  ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[18]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.092     ; 0.437      ;
; 8.270  ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.437      ;
; 8.270  ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[27]                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.091     ; 0.437      ;
; 8.342  ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                           ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.811        ; -0.085     ; 0.371      ;
; 10.057 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.696      ;
; 10.121 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.152      ; 7.639      ;
; 10.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.591      ;
; 10.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 7.389      ;
; 10.196 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.557      ;
; 10.206 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.547      ;
; 10.231 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.331      ;
; 10.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.042     ; 7.332      ;
; 10.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.294      ;
; 10.275 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 7.284      ;
; 10.279 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 7.280      ;
; 10.289 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.275      ;
; 10.294 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.459      ;
; 10.295 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.039     ; 7.274      ;
; 10.309 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 7.250      ;
; 10.318 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.430      ;
; 10.322 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.154      ; 7.440      ;
; 10.326 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.236      ;
; 10.334 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.237      ;
; 10.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.226      ;
; 10.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.222      ;
; 10.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.211      ;
; 10.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]~_Duplicate_7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.400      ;
; 10.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.218      ;
; 10.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.208      ;
; 10.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.152      ; 7.402      ;
; 10.360 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.204      ;
; 10.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.144      ; 7.384      ;
; 10.370 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.192      ;
; 10.375 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.189      ;
; 10.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.185      ;
; 10.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.147      ; 7.373      ;
; 10.390 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.039     ; 7.179      ;
; 10.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.170      ;
; 10.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.166      ;
; 10.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.354      ;
; 10.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.162      ;
; 10.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.162      ;
; 10.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.162      ;
; 10.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.162      ;
; 10.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]_OTERM229                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.160      ;
; 10.409 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]_OTERM185                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.155      ;
; 10.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]_OTERM265                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.154      ;
; 10.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]_OTERM233                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.151      ;
; 10.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.325      ;
; 10.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]_OTERM165                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 7.147      ;
; 10.425 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]_OTERM213                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.137      ;
; 10.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.049     ; 7.133      ;
; 10.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.140      ; 7.321      ;
; 10.428 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]_OTERM249                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.044     ; 7.136      ;
; 10.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|DATA_OUT[0]~18_OTERM151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.131      ;
; 10.432 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.151      ; 7.327      ;
; 10.433 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.320      ;
; 10.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.046     ; 7.127      ;
; 10.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.040     ; 7.133      ;
; 10.443 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; 0.145      ; 7.310      ;
+--------+------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.181  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.371        ; 0.645      ; 0.662      ;
; 38.654 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.330     ; 3.868      ;
; 38.843 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.338     ; 3.671      ;
; 39.100 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.161     ; 3.591      ;
; 39.105 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.161     ; 3.586      ;
; 39.184 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.161     ; 3.507      ;
; 39.257 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.161     ; 3.434      ;
; 39.420 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.161     ; 3.271      ;
; 39.509 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.151     ; 3.192      ;
; 39.515 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.151     ; 3.186      ;
; 39.546 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 3.158      ;
; 39.557 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.149     ; 3.146      ;
; 39.562 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.149     ; 3.141      ;
; 39.604 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.148     ; 3.100      ;
; 39.608 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.151     ; 3.093      ;
; 39.656 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.149     ; 3.047      ;
; 39.659 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.151     ; 3.042      ;
; 39.695 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.924      ;
; 39.706 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.149     ; 2.997      ;
; 39.749 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.953      ;
; 39.754 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.948      ;
; 39.793 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.826      ;
; 39.816 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.149     ; 2.887      ;
; 39.829 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.790      ;
; 39.833 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.869      ;
; 39.837 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.782      ;
; 39.854 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.765      ;
; 39.878 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.151     ; 2.823      ;
; 39.906 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.796      ;
; 39.991 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.628      ;
; 39.991 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.667       ; 1.965      ; 3.628      ;
; 39.997 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.150     ; 2.705      ;
; 40.164 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.158     ; 2.530      ;
; 40.320 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.153     ; 2.379      ;
; 40.445 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.153     ; 2.254      ;
; 41.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.019     ; 0.441      ;
; 41.193 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 41.666       ; -0.019     ; 0.441      ;
; 78.950 ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.020     ; 5.549      ;
; 79.036 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 4.243      ;
; 79.118 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 4.161      ;
; 79.186 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 4.098      ;
; 79.190 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 4.089      ;
; 79.198 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 4.081      ;
; 79.203 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 4.076      ;
; 79.272 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 4.012      ;
; 79.284 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 4.000      ;
; 79.320 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.964      ;
; 79.328 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.956      ;
; 79.345 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.939      ;
; 79.349 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.930      ;
; 79.352 ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.041     ; 3.927      ;
; 79.370 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.914      ;
; 79.406 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.878      ;
; 79.414 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.870      ;
; 79.414 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.870      ;
; 79.431 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.853      ;
; 79.482 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.802      ;
; 79.482 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.802      ;
; 79.496 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.788      ;
; 79.550 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.734      ;
; 79.558 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.726      ;
; 79.568 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.716      ;
; 79.568 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.716      ;
; 79.575 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.709      ;
; 79.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.572      ;
; 79.712 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 3.572      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.033 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.251      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.051 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.233      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.101 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.183      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.119 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.165      ;
; 81.169 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.115      ;
; 81.169 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                                         ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 83.333       ; -0.036     ; 2.115      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.392 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.958        ; -0.961     ; 0.543      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 2.829 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.405        ; -0.961     ; 0.543      ;
; 5.475 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 3.217      ;
; 5.554 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 3.138      ;
; 5.635 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 3.014      ;
; 5.635 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 3.014      ;
; 5.640 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 3.008      ;
; 5.640 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 3.008      ;
; 5.662 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 3.030      ;
; 5.688 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.045     ; 3.017      ;
; 5.726 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.940      ;
; 5.728 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.045     ; 2.977      ;
; 5.764 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 2.930      ;
; 5.798 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.849      ;
; 5.798 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.849      ;
; 5.805 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.861      ;
; 5.806 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.860      ;
; 5.810 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.856      ;
; 5.814 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.861      ;
; 5.817 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.851      ;
; 5.818 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.857      ;
; 5.821 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.847      ;
; 5.826 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.867      ;
; 5.826 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.846      ;
; 5.832 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.838      ;
; 5.836 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.834      ;
; 5.841 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|addr_reg[0]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.851      ;
; 5.855 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.794      ;
; 5.855 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.794      ;
; 5.860 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.788      ;
; 5.860 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.788      ;
; 5.864 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.805      ;
; 5.870 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.872      ;
; 5.874 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.868      ;
; 5.883 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.766      ;
; 5.883 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.766      ;
; 5.888 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.760      ;
; 5.888 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.760      ;
; 5.890 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.049     ; 2.811      ;
; 5.891 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.801      ;
; 5.896 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.773      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.055     ; 2.842      ;
; 5.900 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.769      ;
; 5.905 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.788      ;
; 5.905 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.767      ;
; 5.906 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.787      ;
; 5.908 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.762      ;
; 5.910 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.057     ; 2.783      ;
; 5.911 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.760      ;
; 5.912 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.758      ;
; 5.913 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.036     ; 2.848      ;
; 5.915 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.756      ;
; 5.934 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.741      ;
; 5.936 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.090     ; 2.712      ;
; 5.943 ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                           ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.679      ;
; 5.945 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.747      ;
; 5.946 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.722      ;
; 5.950 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.718      ;
; 5.961 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.709      ;
; 5.961 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.707      ;
; 5.962 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.709      ;
; 5.964 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[2]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.044     ; 2.742      ;
; 5.967 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[3]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.056     ; 2.727      ;
; 5.968 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                               ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.084     ; 2.698      ;
; 5.969 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.049     ; 2.732      ;
; 5.970 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.698      ;
; 5.975 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.043     ; 2.779      ;
; 5.975 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.702      ;
; 5.979 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.073     ; 2.698      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.082     ; 2.687      ;
; 5.981 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.058     ; 2.711      ;
; 5.984 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|cas_n_reg                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.049     ; 2.717      ;
; 5.991 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.678      ;
; 5.994 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.677      ;
; 5.995 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[6]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.081     ; 2.674      ;
; 5.997 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[7]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.674      ;
; 5.998 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|addr_reg[8]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.676      ;
; 6.002 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|ba_reg[1]                                                                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.045     ; 2.703      ;
; 6.004 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.671      ;
; 6.006 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|addr_reg[4]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.076     ; 2.668      ;
; 6.007 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.666      ;
; 6.007 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.079     ; 2.664      ;
; 6.009 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.077     ; 2.664      ;
; 6.011 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.046     ; 2.693      ;
; 6.013 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                               ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.078     ; 2.659      ;
; 6.015 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.046     ; 2.689      ;
; 6.018 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.629      ;
; 6.018 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.091     ; 2.629      ;
; 6.018 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.657      ;
; 6.020 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                               ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.080     ; 2.650      ;
; 6.022 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                         ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.653      ;
; 6.029 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                         ; sdram_statemachine:sdram_adaptor|addr_reg[5]                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.075     ; 2.646      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack     ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 13.668    ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 15.493       ; -0.961     ; 0.792      ;
; 88102.579 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 3.009      ;
; 88102.579 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 3.009      ;
; 88102.582 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.997      ;
; 88102.582 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.997      ;
; 88102.675 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.904      ;
; 88102.675 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.904      ;
; 88102.794 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.785      ;
; 88102.880 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.699      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.101 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.476      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.122 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.455      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.194 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.383      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.205 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 2.372      ;
; 88103.335 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 2.253      ;
; 88103.349 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.230      ;
; 88103.349 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.230      ;
; 88103.431 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 2.157      ;
; 88103.485 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 2.094      ;
; 88103.650 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 1.929      ;
; 88103.692 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.896      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.695 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.893      ;
; 88103.726 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.851      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.768 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.809      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.781 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.807      ;
; 88103.871 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.048     ; 1.706      ;
; 88104.016 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.572      ;
; 88104.102 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.486      ;
; 88104.234 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.046     ; 1.345      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.414 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.174      ;
; 88104.509 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.079      ;
; 88104.509 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.079      ;
; 88104.512 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.076      ;
; 88104.522 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.066      ;
; 88104.522 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.066      ;
; 88104.525 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.063      ;
; 88104.570 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 1.018      ;
; 88104.603 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.985      ;
; 88104.603 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.985      ;
; 88104.606 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.982      ;
; 88104.609 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.979      ;
; 88104.609 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.979      ;
; 88104.612 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.976      ;
; 88104.709 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.879      ;
; 88104.811 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.777      ;
; 88104.819 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 88105.638    ; -0.037     ; 0.769      ;
+-----------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_27[0]'                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 35.614 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.373      ;
; 35.683 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.304      ;
; 35.699 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.288      ;
; 35.701 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.286      ;
; 35.754 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.233      ;
; 35.766 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.221      ;
; 35.768 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.219      ;
; 35.820 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.167      ;
; 35.823 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.164      ;
; 35.827 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.160      ;
; 35.835 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.152      ;
; 35.835 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.152      ;
; 35.841 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.146      ;
; 35.842 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.145      ;
; 35.887 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.100      ;
; 35.910 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.077      ;
; 35.911 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.076      ;
; 35.914 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.073      ;
; 35.947 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.040      ;
; 35.949 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.038      ;
; 35.950 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.037      ;
; 35.954 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.033      ;
; 35.961 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 1.026      ;
; 36.012 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.975      ;
; 36.062 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.925      ;
; 36.065 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.922      ;
; 36.066 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.921      ;
; 36.071 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.916      ;
; 36.072 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.915      ;
; 36.076 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.911      ;
; 36.076 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.911      ;
; 36.077 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.910      ;
; 36.081 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.906      ;
; 36.088 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.899      ;
; 36.126 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.861      ;
; 36.131 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.856      ;
; 36.144 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.843      ;
; 36.146 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.841      ;
; 36.146 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.841      ;
; 36.147 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.840      ;
; 36.149 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.838      ;
; 36.152 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.835      ;
; 36.152 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.835      ;
; 36.156 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.831      ;
; 36.161 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.826      ;
; 36.168 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.819      ;
; 36.174 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.813      ;
; 36.198 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.789      ;
; 36.220 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.767      ;
; 36.223 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.764      ;
; 36.226 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.761      ;
; 36.228 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.759      ;
; 36.229 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.758      ;
; 36.232 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.755      ;
; 36.236 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.751      ;
; 36.254 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.733      ;
; 36.365 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.622      ;
; 36.437 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.550      ;
; 36.454 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.533      ;
; 36.628 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 37.037       ; -0.037     ; 0.359      ;
+--------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                     ; Launch Clock                                                          ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                         ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.017        ; 1.299      ; 0.574      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C2_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C4_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C0_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C3_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_data_state                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                    ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.197  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.198  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.200  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                             ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.320      ;
; 0.201  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.321      ;
; 0.201  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.321      ;
; 0.204  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.204  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.205  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.208  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.328      ;
; 0.210  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                    ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.330      ;
; 0.213  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                           ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.333      ;
; 0.231  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.351      ;
; 0.235  ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                               ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                               ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.355      ;
; 0.257  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.377      ;
; 0.267  ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                        ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                        ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.269  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                   ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.389      ;
; 0.273  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.393      ;
; 0.274  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.394      ;
; 0.283  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                            ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.403      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                           ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296  ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                      ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.297  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.297  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.420      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.301  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_ena_state                                                                  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|C1_data_state                                                                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
; 0.304  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.304  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.304  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.305  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                        ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                 ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305  ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                                ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.111 ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                                                                                                                                                          ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 0.313      ;
; 0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.473      ;
; 0.148 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.477      ;
; 0.148 ; scandoubler:scandoubler1|colour_reg[4]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.469      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.478      ;
; 0.149 ; scandoubler:scandoubler1|colour_reg[2]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.470      ;
; 0.152 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.477      ;
; 0.152 ; scandoubler:scandoubler1|colour_reg[5]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.473      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.483      ;
; 0.155 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.479      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.485      ;
; 0.158 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.483      ;
; 0.158 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.483      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.483      ;
; 0.160 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.484      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.485      ;
; 0.163 ; scandoubler:scandoubler1|colour_reg[0]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.484      ;
; 0.163 ; scandoubler:scandoubler1|colour_reg[1]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.484      ;
; 0.164 ; scandoubler:scandoubler1|colour_reg[6]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.485      ;
; 0.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0~porta_datain_reg0 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.494      ;
; 0.166 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.495      ;
; 0.167 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[3]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.494      ;
; 0.167 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.492      ;
; 0.168 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.493      ;
; 0.168 ; scandoubler:scandoubler1|colour_reg[3]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.489      ;
; 0.169 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.493      ;
; 0.169 ; scandoubler:scandoubler1|colour_reg[7]                                                                                                                                                                    ; scandoubler:scandoubler1|gtia_palette:palette4|altsyncram:Mux21_rtl_0|altsyncram_tt01:auto_generated|ram_block1a0~porta_address_reg0                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.490      ;
; 0.170 ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                                                                                                                                                         ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[14]                                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 0.372      ;
; 0.170 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.499      ;
; 0.170 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.494      ;
; 0.171 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.500      ;
; 0.171 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[6]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.498      ;
; 0.172 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[5]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.499      ;
; 0.174 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.503      ;
; 0.175 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[4]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.502      ;
; 0.176 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.501      ;
; 0.176 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.501      ;
; 0.178 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]_OTERM287                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]_OTERM275                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.183 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_datain_reg0          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.507      ;
; 0.184 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.513      ;
; 0.185 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|cntr_8rf:cntr1|counter_reg_bit[0]                                                             ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.512      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_reg                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_reg                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_shift_reg[9]                                                                                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[0]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[1]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[2]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serin_bitcount_reg[3]                                                                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_clock_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_clock_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_shift_reg[9]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serout_shift_reg[9]                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_out_reg                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|serial_out_reg                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|shift_pressed_reg                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[4]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[4]                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|control_pressed_reg                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_freezer_reg                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                                                                                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                       ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_27[0]'                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.193 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.314      ;
; 0.298 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.419      ;
; 0.306 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.427      ;
; 0.364 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.485      ;
; 0.426 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.547      ;
; 0.435 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.556      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.575      ;
; 0.464 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.585      ;
; 0.465 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.468 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.489 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.610      ;
; 0.490 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.611      ;
; 0.498 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.619      ;
; 0.499 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.620      ;
; 0.501 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.622      ;
; 0.508 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.629      ;
; 0.509 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.518 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.639      ;
; 0.527 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.648      ;
; 0.528 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.649      ;
; 0.528 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.649      ;
; 0.530 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.651      ;
; 0.532 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.653      ;
; 0.532 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.653      ;
; 0.533 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.654      ;
; 0.553 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.674      ;
; 0.562 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.683      ;
; 0.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.685      ;
; 0.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.685      ;
; 0.564 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.685      ;
; 0.571 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.692      ;
; 0.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.694      ;
; 0.573 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.694      ;
; 0.575 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.696      ;
; 0.578 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.699      ;
; 0.589 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.710      ;
; 0.590 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.711      ;
; 0.590 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.711      ;
; 0.594 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.715      ;
; 0.594 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.715      ;
; 0.628 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.749      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.758      ;
; 0.637 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.758      ;
; 0.639 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.760      ;
; 0.639 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.760      ;
; 0.646 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.767      ;
; 0.646 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.767      ;
; 0.665 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.786      ;
; 0.665 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.786      ;
; 0.666 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.787      ;
; 0.666 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.787      ;
; 0.670 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.791      ;
; 0.670 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.791      ;
; 0.731 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.852      ;
; 0.770 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.891      ;
; 0.772 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.893      ;
; 0.772 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.893      ;
; 0.773 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.894      ;
; 0.773 ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; CLOCK_27[0]  ; CLOCK_27[0] ; 0.000        ; 0.037      ; 0.894      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                     ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.203 ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.324      ;
; 0.293 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.414      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.294 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.415      ;
; 0.295 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.416      ;
; 0.298 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
; 0.303 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.304 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.424      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.425      ;
; 0.305 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.426      ;
; 0.306 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.306 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.426      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.307 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.427      ;
; 0.308 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.428      ;
; 0.308 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.429      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.310 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.431      ;
; 0.311 ; sdram_statemachine:sdram_adaptor|request_sreg                 ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.092      ; 0.506      ;
; 0.316 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.437      ;
; 0.317 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
; 0.320 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.441      ;
; 0.331 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.452      ;
; 0.398 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.518      ;
; 0.441 ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.562      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.568      ;
; 0.449 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.569      ;
; 0.450 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.570      ;
; 0.451 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.572      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.452 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.455 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.458 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.580      ;
; 0.460 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.461 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.581      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.462 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.582      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.583      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.583      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.583      ;
; 0.463 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.584      ;
; 0.464 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.584      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.585      ;
; 0.465 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.586      ;
; 0.466 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.587      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.587      ;
; 0.467 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.588      ;
; 0.468 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.589      ;
; 0.470 ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.591      ;
; 0.471 ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.592      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.509 ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.630      ;
; 0.511 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.631      ;
; 0.512 ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.632      ;
; 0.513 ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.633      ;
+-------+---------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.307      ;
; 0.200 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.321      ;
; 0.200 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.321      ;
; 0.200 ; user_io:my_user_io|ps2_r_inc                                                ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.321      ;
; 0.207 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.328      ;
; 0.217 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.338      ;
; 0.237 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.358      ;
; 0.245 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.366      ;
; 0.265 ; user_io:my_user_io|ps2_tx_byte[5]                                           ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.386      ;
; 0.266 ; user_io:my_user_io|ps2_tx_byte[6]                                           ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.387      ;
; 0.266 ; user_io:my_user_io|ps2_tx_byte[2]                                           ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.387      ;
; 0.266 ; user_io:my_user_io|ps2_tx_byte[1]                                           ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.387      ;
; 0.267 ; user_io:my_user_io|ps2_tx_byte[3]                                           ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.388      ;
; 0.268 ; user_io:my_user_io|ps2_tx_byte[4]                                           ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.389      ;
; 0.310 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.431      ;
; 0.311 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.432      ;
; 0.316 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.437      ;
; 0.333 ; user_io:my_user_io|ps2_tx_byte[7]                                           ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.454      ;
; 0.346 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.467      ;
; 0.347 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.468      ;
; 0.348 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.469      ;
; 0.349 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.470      ;
; 0.350 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.471      ;
; 0.351 ; user_io:my_user_io|ps2_kbd_data                                             ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.472      ;
; 0.354 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.475      ;
; 0.356 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.477      ;
; 0.398 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.519      ;
; 0.398 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.519      ;
; 0.398 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.519      ;
; 0.430 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.551      ;
; 0.434 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.555      ;
; 0.439 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.560      ;
; 0.454 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.575      ;
; 0.457 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.578      ;
; 0.487 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.608      ;
; 0.495 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.616      ;
; 0.500 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.621      ;
; 0.504 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.625      ;
; 0.505 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.626      ;
; 0.505 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.626      ;
; 0.530 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.651      ;
; 0.530 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.651      ;
; 0.537 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.658      ;
; 0.562 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.683      ;
; 0.570 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.691      ;
; 0.641 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.762      ;
; 0.666 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.787      ;
; 0.672 ; user_io:my_user_io|ps2_tx_state[0]                                          ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.793      ;
; 0.752 ; user_io:my_user_io|ps2_tx_state[1]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.873      ;
; 0.755 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.876      ;
; 0.758 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.879      ;
; 0.760 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.881      ;
; 0.761 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.882      ;
; 0.763 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.884      ;
; 0.765 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.886      ;
; 0.771 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.892      ;
; 0.773 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.894      ;
; 0.774 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.895      ;
; 0.786 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.907      ;
; 0.790 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.911      ;
; 0.793 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.914      ;
; 0.797 ; user_io:my_user_io|ps2_tx_state[3]                                          ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.918      ;
; 0.870 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.991      ;
; 0.870 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 0.991      ;
; 0.900 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.021      ;
; 0.948 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.069      ;
; 1.001 ; user_io:my_user_io|ps2_parity                                               ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.048      ; 1.133      ;
; 1.011 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.132      ;
; 1.132 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.262      ;
; 1.187 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.308      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.351      ;
; 1.221 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.342      ;
; 1.253 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.374      ;
; 1.317 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_r_inc                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.447      ;
; 1.433 ; user_io:my_user_io|Equal5~0_OTERM1                                          ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 1.563      ;
; 1.464 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; -0.824     ; 0.717      ;
; 1.508 ; user_io:my_user_io|ps2_tx_byte[0]                                           ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.048      ; 1.640      ;
; 1.527 ; user_io:my_user_io|ps2_rptr[1]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.648      ;
; 1.559 ; user_io:my_user_io|ps2_rptr[0]                                              ; user_io:my_user_io|ps2_parity                                                                                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.037      ; 1.680      ;
; 1.726 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_kbd_data                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.048      ; 1.858      ;
; 1.777 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.048      ; 1.909      ;
; 1.778 ; user_io:my_user_io|ps2_rptr[2]                                              ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.048      ; 1.910      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
; 1.992 ; user_io:my_user_io|ps2_tx_state[2]                                          ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.046      ; 2.122      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 8.109 ; switch_pal_ntsc:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -6.853       ; -0.824     ; 0.499      ;
+-------+-----------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'CLOCK_27[0]'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.357 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.748      ; 2.161      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
; -0.340 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.179        ; 1.750      ; 2.146      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 6.058 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[4]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.123     ; 2.569      ;
; 6.058 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[6]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.131     ; 2.561      ;
; 6.059 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.135     ; 2.556      ;
; 6.059 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[5]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.125     ; 2.566      ;
; 6.059 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[9]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.564      ;
; 6.060 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[1]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 2.552      ;
; 6.061 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.189     ; 2.498      ;
; 6.062 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.192     ; 2.494      ;
; 6.064 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[11]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.124     ; 2.562      ;
; 6.065 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|udqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.558      ;
; 6.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[7]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.557      ;
; 6.067 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[8]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.126     ; 2.557      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.552      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.130     ; 2.552      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.550      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[9]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.132     ; 2.550      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.555      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.127     ; 2.555      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.554      ;
; 6.068 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.128     ; 2.554      ;
; 6.069 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.552      ;
; 6.069 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]               ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.129     ; 2.552      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.494      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 2.497      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.492      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.186     ; 2.492      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.496      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.182     ; 2.496      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.181     ; 2.497      ;
; 6.070 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.184     ; 2.494      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[15]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 2.494      ;
; 6.071 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[14]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.183     ; 2.494      ;
; 6.072 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.573      ;
; 6.072 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[2]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.574      ;
; 6.072 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[10]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.573      ;
; 6.073 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[0]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.105     ; 2.572      ;
; 6.073 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[1]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.573      ;
; 6.073 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|addr_reg[3]                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.574      ;
; 6.080 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.567      ;
; 6.080 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.567      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.566      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.103     ; 2.566      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.562      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.107     ; 2.562      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.106     ; 2.563      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.565      ;
; 6.081 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.104     ; 2.565      ;
; 6.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 2.509      ;
; 6.082 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 2.509      ;
; 6.083 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 2.508      ;
; 6.083 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.157     ; 2.508      ;
; 6.094 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.605      ;
; 6.094 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.098     ; 2.605      ;
; 6.159 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.144     ; 2.435      ;
; 6.160 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.147     ; 2.431      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.431      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.139     ; 2.431      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.429      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.141     ; 2.429      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.434      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.136     ; 2.434      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.433      ;
; 6.168 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.137     ; 2.433      ;
; 6.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 2.431      ;
; 6.169 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.138     ; 2.431      ;
; 6.180 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 2.446      ;
; 6.180 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 2.446      ;
; 6.181 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 2.445      ;
; 6.181 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.112     ; 2.445      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.393      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.393      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.404      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.393      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.404      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.404      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.089     ; 2.404      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.100     ; 2.393      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.097     ; 2.396      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.093     ; 2.400      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
; 6.304 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.810        ; -0.102     ; 2.391      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                   ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                                                                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 14.588 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 2.988      ;
; 14.588 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 2.988      ;
; 14.589 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.033     ; 2.986      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.591 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.037     ; 2.980      ;
; 14.614 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 2.963      ;
; 14.614 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.031     ; 2.963      ;
; 14.615 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.032     ; 2.961      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.617 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.036     ; 2.955      ;
; 14.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_enable~0_OTERM3                             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 2.780      ;
; 14.739 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.089     ; 2.780      ;
; 14.740 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.090     ; 2.778      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[6]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[7]                                            ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.752 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot4_reg[7]                                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.084     ; 2.772      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[5]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 2.784      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[6]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 2.784      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[7]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 2.784      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[4]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.051     ; 2.784      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 2.780      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 2.780      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.781      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 2.780      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.773 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.060     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|S[3]                              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.050     ; 2.784      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.056     ; 2.778      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.058     ; 2.776      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[4]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 2.779      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.058     ; 2.776      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[7]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.055     ; 2.779      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.058     ; 2.776      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[3]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.058     ; 2.776      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[7]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.059     ; 2.775      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[2]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[4]                                         ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.057     ; 2.777      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[1]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[2]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[3]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[4]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[5]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[6]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[7]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[8]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[9]                                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[10]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[11]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[12]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
; 14.774 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_end_reg[13]                                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.621       ; -0.054     ; 2.780      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'CLOCK_27[0]'                                                                                                                                                                                                                                ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                              ; To Node                                                   ; Launch Clock                                                          ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.378 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.197      ; 2.022      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
; -0.371 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0] ; 0.029        ; 2.200      ; 2.032      ;
+--------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 0.686 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|dffe4                                                                 ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 0.978      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 1.115      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a55 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a54 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a53 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a52 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a51 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a50 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a49 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a48 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a27 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a26 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a25 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a24 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a23 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a22 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a21 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a20 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a19 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a18 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a17 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a16 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a7  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a6  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a5  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a4  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a3  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a2  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a1  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a0  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 1.143      ;
; 1.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.270      ; 2.025      ;
; 1.671 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.270      ; 2.025      ;
; 1.672 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.267      ; 2.023      ;
; 1.672 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.267      ; 2.023      ;
; 1.672 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.267      ; 2.023      ;
; 1.674 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.022      ;
; 1.723 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                                                                                                                                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.228      ; 2.035      ;
; 1.723 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.228      ; 2.035      ;
; 1.724 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 2.033      ;
; 1.724 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 2.033      ;
; 1.724 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                                                                                                  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 2.033      ;
; 1.726 ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 2.032      ;
; 1.839 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.289      ; 2.212      ;
; 1.839 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.289      ; 2.212      ;
; 1.839 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.289      ; 2.212      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                                                                                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[12]                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[5]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[6]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                                                                                                                                                        ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.024      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[13]                                                                                                                                                          ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[13]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[12]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[11]                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.845 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                                   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.021      ;
; 1.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 2.029      ;
; 1.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.022      ;
; 1.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.025      ;
; 1.846 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.025      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                              ; To Node                                                       ; Launch Clock                                                          ; Latch Clock                                                           ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.116      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.116      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.116      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.116      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.111      ;
; 1.919 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cke_reg                      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.094      ; 2.116      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.103      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.103      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.104      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.103      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.103      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.106      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.103      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|reply_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.109      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 2.112      ;
; 1.920 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 2.109      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 1.921 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.104      ;
; 2.005 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.164      ;
; 2.005 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 2.164      ;
; 2.006 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.164      ;
; 2.006 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 2.164      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 2.153      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.047      ; 2.153      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.156      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.050      ; 2.156      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 2.155      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.049      ; 2.155      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.048      ; 2.154      ;
; 2.023 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.048      ; 2.154      ;
; 2.024 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 2.152      ;
; 2.024 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.045      ; 2.152      ;
; 2.029 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.042      ; 2.154      ;
; 2.030 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.039      ; 2.152      ;
; 2.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.292      ;
; 2.105 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.292      ;
; 2.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.287      ;
; 2.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 2.287      ;
; 2.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[0]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.283      ;
; 2.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|we_n_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.286      ;
; 2.126 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ldqm_reg                     ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.286      ;
; 2.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.287      ;
; 2.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 2.287      ;
; 2.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ras_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 2.283      ;
; 2.127 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|cas_n_reg                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 2.284      ;
; 2.134 ; switch_pal_ntsc:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; sdram_statemachine:sdram_adaptor|ba_reg[1]                    ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 2.292      ;
+-------+------------------------------------------------------------------------+---------------------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                        ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[0]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[10]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[11]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[12]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[13]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[15]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[1]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[25]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[28]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[29]             ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[2]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[3]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[4]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[5]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[6]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[7]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[9]              ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|reply_reg                    ;
; 4.186 ; 4.402        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]           ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cke_reg                      ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[14]             ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[8]              ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[0]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[10]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[11]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[12]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[13]                ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[1]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[2]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[3]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[4]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[5]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[6]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[7]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[8]                 ;
; 4.187 ; 4.403        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|delay_reg[9]                 ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[0]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[10] ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[1]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[2]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[3]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[4]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[5]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[6]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[7]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[8]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|cycles_since_refresh_reg[9]  ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[16]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[17]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[18]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[19]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[20]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[21]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[26]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[27]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[30]             ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[0]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[10]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[11]      ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[1]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[2]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[3]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[4]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[5]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[6]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[7]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[8]       ;
; 4.189 ; 4.405        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|refresh_pending_reg[9]       ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[22]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[23]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[24]             ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|data_out_reg[31]             ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_4   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_5   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_6   ;
; 4.190 ; 4.345        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_7   ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]           ;
; 4.190 ; 4.406        ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]           ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg                ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_1   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_8   ;
; 4.192 ; 4.347        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_9   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_10  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_11  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_12  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_13  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_14  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_15  ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_2   ;
; 4.193 ; 4.348        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_output_reg~_Duplicate_3   ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[4]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[5]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[6]                 ;
; 4.195 ; 4.350        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[7]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[0]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[1]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[8]                 ;
; 4.197 ; 4.352        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[9]                 ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[10]                ;
; 4.198 ; 4.353        ; 0.155          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_statemachine:sdram_adaptor|dq_in_reg[11]                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                     ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 4.331 ; 4.400        ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.357 ; 4.410        ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 4.400 ; 4.400        ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 4.410 ; 4.410        ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                         ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type            ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                           ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_address_reg0    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_address_reg0                                                                    ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                           ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                            ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                  ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_address_reg0             ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_9l31:auto_generated|a_dpfifo_gr31:dpfifo|altsyncram_aj81:FIFOram|ram_block1a0~porta_we_reg                   ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_address_reg0                                 ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_jf41:auto_generated|ram_block1a0~porta_we_reg                                       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~portb_address_reg0    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0                                                                                       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~portb_address_reg0                                                                    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_address_reg0                                                                                              ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a0~porta_we_reg                                                                                                    ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                            ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                          ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_address_reg0           ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_rj31:auto_generated|a_dpfifo_2q31:dpfifo|altsyncram_eg81:FIFOram|ram_block1a0~porta_we_reg                 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a10                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a11                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a12                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a13                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a14                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a15                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a28                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a29                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a30                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a31                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a32                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a33                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a34                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a35                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a36                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a37                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a38                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a39                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a40                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a41                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a42                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a43                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a44                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a45                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a46                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a47                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a56                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a57                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a58                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a59                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a60                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a61                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a62                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a63                      ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a8~porta_datain_reg0     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_j7n:auto_generated|altsyncram_sa61:altsyncram4|ram_block7a9                       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|delay_line:hsync_delay|altshift_taps:shift_reg_rtl_0|shift_taps_lnm:auto_generated|altsyncram_v6b1:altsyncram2|ram_block5a0~porta_datain_reg0                                                                     ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_address_reg0                                                                                              ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; scandoubler:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_0h81:auto_generated|ram_block1a4~porta_we_reg                                                                                                    ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_69a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                           ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_fi41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                            ;
+-------+--------------+----------------+-----------------+-----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.300 ; 16.300       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.310 ; 16.310       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.314 ; 16.314       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.316 ; 16.316       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 16.321 ; 16.321       ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 16.331 ; 16.331       ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_27[0]'                                                                                                               ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock       ; Clock Edge ; Target                                                                         ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 17.785 ; 17.969       ; 0.184          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 17.928 ; 17.928       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 17.929 ; 17.929       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 17.960 ; 17.960       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 17.964 ; 17.964       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 17.970 ; 17.970       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 17.971 ; 17.971       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 17.972 ; 17.972       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|i                                                            ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 18.851 ; 19.067       ; 0.216          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|inclk[0]                                              ;
; 19.064 ; 19.064       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~inputclkctrl|outclk                                                ;
; 19.066 ; 19.066       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]                     ;
; 19.067 ; 19.067       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[0]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[1]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[2]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[3]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[4]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[5]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[6]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_count_reg[7]|clk                                          ;
; 19.072 ; 19.072       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; zpu|config_regs|tick_toggle_reg|clk                                            ;
; 19.077 ; 19.077       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]~input|o                                                            ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]                       ;
; 19.107 ; 19.107       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; reconfig_pll|altpll_component|auto_generated|pll1|observablevcoout             ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 19.108 ; 19.108       ; 0.000          ; High Pulse Width ; CLOCK_27[0] ; Rise       ; pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 33.037 ; 37.037       ; 4.000          ; Port Rate        ; CLOCK_27[0] ; Rise       ; CLOCK_27[0]                                                                    ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                      ;
; 35.037 ; 37.037       ; 2.000          ; Min Period       ; CLOCK_27[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                        ;
+--------+--------------+----------------+------------------+-------------+------------+--------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'reconfig_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 40.634 ; 41.644       ; 1.010          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 40.678 ; 41.688       ; 1.010          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|pll_pal:generic_pll|altpll:altpll_component|pll_pal_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                       ;
; 41.417 ; 41.647       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 41.418 ; 41.648       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 41.419 ; 41.649       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|altsyncram:altsyncram4|altsyncram_72m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 41.420 ; 41.650       ; 0.230          ; Low Pulse Width  ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|altsyncram:altsyncram4|altsyncram_cul3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 41.440 ; 41.656       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate3_state                                                                                   ;
; 41.440 ; 41.656       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate3_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_enable_reg                                                                                                                                                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[0]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[10]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[11]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[1]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                                                                              ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[2]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[3]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[4]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[5]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[6]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[7]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[8]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_pause_counter_reg[9]                                                                                                                                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|reset_n_reg                                                                                                                                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|areset_state                                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate2_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|configupdate_state                                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|idle_state                                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_init_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_post_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_data_state                                                                               ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_seq_ena_state                                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reconfig_wait_state                                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_6bu:video_pll_reconfig_pllrcfg_6bu_component|reset_state                                                                                           ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C0_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C1_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C2_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C3_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_data_state                                                                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|C4_ena_state                                                                          ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|areset_init_state_1                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate2_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|configupdate_state                                                                    ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|idle_state                                                                            ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[6]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr12|cntr_tho:auto_generated|counter_reg_bit[7]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[0]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[1]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[2]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[3]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[4]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[5]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[6]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|lpm_counter:cntr15|cntr_tho:auto_generated|counter_reg_bit[7]                         ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_counter_state                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_init_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_post_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_seq_ena_state                                                                ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reconfig_wait_state                                                                   ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|reset_state                                                                           ;
; 41.449 ; 41.665       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_b7u:video_pll_reconfig_pal_pllrcfg_b7u_component|tmp_seq_ena_state                                                                     ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[0]                                                                                                                                                                                                       ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[1]                                                                                                                                                                                                       ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[2]                                                                                                                                                                                                       ;
; 41.450 ; 41.666       ; 0.216          ; High Pulse Width ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:pll_switcher|pll_state_reg[3]                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                                         ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack     ; Actual Width ; Required Width ; Type             ; Clock                                                                 ; Clock Edge ; Target                                                                                                                                ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.600 ; 44052.816    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.601 ; 44052.817    ; 0.216          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
; 44052.635 ; 44052.819    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[3]                                                                                                    ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 44052.636 ; 44052.820    ; 0.184          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 44052.745 ; 44052.814    ; 0.069          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.771 ; 44052.824    ; 0.053          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Fall       ; switch_pal_ntsc:pll_switcher|clkctrl:\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.814 ; 44052.814    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.815 ; 44052.815    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.816 ; 44052.816    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_parity|clk                                                                                                             ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_r_inc|clk                                                                                                              ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[0]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[1]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_rptr[2]|clk                                                                                                            ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[0]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[1]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[2]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[3]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[4]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[5]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[6]|clk                                                                                                         ;
; 44052.822 ; 44052.822    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_byte[7]|clk                                                                                                         ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|Equal5~0_NEW_REG0|clk                                                                                                      ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_kbd_data|clk                                                                                                           ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[0]|clk                                                                                                        ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[1]|clk                                                                                                        ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[2]|clk                                                                                                        ;
; 44052.823 ; 44052.823    ; 0.000          ; High Pulse Width ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; my_user_io|ps2_tx_state[3]|clk                                                                                                        ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 44052.824 ; 44052.824    ; 0.000          ; Low Pulse Width  ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; pll_switcher|\GEN_CLKCTRL:3:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|Equal5~0_OTERM1                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_kbd_data                                                                                                       ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_parity                                                                                                         ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_r_inc                                                                                                          ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[0]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[1]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_rptr[2]                                                                                                        ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[0]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[1]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[2]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[3]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[4]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[5]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[6]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_byte[7]                                                                                                     ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[0]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[1]                                                                                                    ;
; 88103.638 ; 88105.638    ; 2.000          ; Min Period       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; user_io:my_user_io|ps2_tx_state[2]                                                                                                    ;
+-----------+--------------+----------------+------------------+-----------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.467 ; 2.019 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.470 ; 2.022 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.472 ; 2.024 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.458 ; 2.016 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.448 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.454 ; 2.006 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.459 ; 2.011 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.460 ; 2.012 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.471 ; 2.023 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.991 ; -1.543 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.980 ; -1.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.978 ; -1.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.978 ; -1.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 1.292  ; 1.163  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 1.165  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 1.165  ; 1.009  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 1.124  ; 0.985  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 1.291  ; 1.162  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 1.276  ; 1.147  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 1.280  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 1.280  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 1.279  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 1.164  ; 1.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 1.292  ; 1.163  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 1.154  ; 0.998  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 1.239  ; 1.151  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.287  ; 1.158  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.271  ; 1.142  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.268  ; 1.139  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.116  ; 0.977  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.116  ; 0.977  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.177  ; 1.021  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.187  ; 1.031  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.264  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.264  ; 1.135  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.279  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.279  ; 1.150  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.108  ; 0.969  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.278  ; 1.149  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.287  ; 1.158  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.117  ; 0.978  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 1.270  ; 1.141  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 1.163  ; 1.007  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 1.162  ; 1.006  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 1.176  ; 1.020  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.966  ; 2.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.890  ; 2.693  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 3.947  ; 3.993  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 4.245  ; 4.503  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 4.245  ; 4.503  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 4.103  ; 4.322  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 3.650  ; 3.752  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 3.889  ; 4.113  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 3.556  ; 3.742  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 3.677  ; 3.896  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 4.559  ; 4.881  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 4.329  ; 4.626  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 4.277  ; 4.574  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 4.149  ; 4.429  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 4.559  ; 4.881  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 4.437  ; 4.718  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 4.458  ; 4.762  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 3.121  ; 2.938  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 4.189  ; 4.457  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 3.642  ; 3.835  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 3.651  ; 3.843  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 4.097  ; 4.350  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 3.770  ; 3.932  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 3.906  ; 3.994  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 4.189  ; 4.457  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 3.545  ; 3.436  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -1.626 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -1.743 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.870  ; 0.741  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.887  ; 0.758  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.864  ; 0.735  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.545  ; 2.329  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.471  ; 2.271  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 3.475  ; 3.530  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 1.774  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.460  ; 2.432  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.375  ; 2.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 2.026  ; 1.954  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 1.989  ; 1.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 1.855  ; 1.773  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 1.774  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.361  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.416  ; 2.400  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.369  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.361  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.625  ; 2.627  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.450  ; 2.423  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.534  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.694  ; 2.507  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 1.893  ; 1.803  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 1.926  ; 1.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 1.893  ; 1.803  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.163  ; 2.114  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.312  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.234  ; 2.199  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.271  ; 2.228  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 3.101  ; 2.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.008 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.127 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------+
; Propagation Delay                                        ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 5.546 ; 5.546 ; 6.298 ; 6.271 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------+
; Minimum Propagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.639 ; 4.522 ; 5.266 ; 5.266 ;
+------------+-------------+-------+-------+-------+-------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                              ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 1.932 ; 1.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 1.939 ; 1.984 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 1.936 ; 1.981 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 1.954 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 1.947 ; 1.999 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 1.957 ; 2.009 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 1.946 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 1.946 ; 1.998 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 1.932 ; 1.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 1.932 ; 1.977 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 1.947 ; 1.992 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 1.947 ; 1.992 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 1.946 ; 1.991 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 1.946 ; 1.991 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 1.955 ; 2.000 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.733 ; 0.733 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.730 ; 0.730 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.748 ; 0.748 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.790 ; 0.790 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.780 ; 0.780 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.726 ; 0.726 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.741 ; 0.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.741 ; 0.741 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.740 ; 0.740 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.749 ; 0.749 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                     ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.009     ; 2.009     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.016     ; 2.016     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.013     ; 2.013     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.031     ; 2.031     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.041     ; 2.041     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.030     ; 2.030     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.009     ; 2.009     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.009     ; 2.009     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.024     ; 2.024     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.024     ; 2.024     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.023     ; 2.023     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.023     ; 2.023     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.032     ; 2.032     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                             ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.764     ; 0.992     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.761     ; 0.989     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.779     ; 1.007     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.821     ; 1.065     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.811     ; 1.055     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.757     ; 0.985     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.772     ; 1.000     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.772     ; 1.000     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.771     ; 0.999     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.780     ; 1.008     ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-----------+-----------+------------+-----------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                  ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Clock                                                                  ; Setup   ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Worst-case Slack                                                       ; -4.851  ; -1.583 ; -1.162   ; -0.429  ; 4.093               ;
;  CLOCK_27[0]                                                           ; 33.845  ; 0.186  ; -1.162   ; -0.429  ; 17.785              ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.890   ; 0.186  ; 2.981    ; 1.919   ; 4.093               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.851  ; 0.111  ; 10.890   ; 0.686   ; 8.379               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547  ; 8.109  ; N/A      ; N/A     ; 4.224               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 11.442  ; 0.186  ; N/A      ; N/A     ; 44052.506           ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A     ; N/A    ; N/A      ; N/A     ; 16.274              ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.083  ; -1.583 ; N/A      ; N/A     ; 40.592              ;
; Design-wide TNS                                                        ; -13.194 ; -1.583 ; -10.458  ; -3.861  ; 0.0                 ;
;  CLOCK_27[0]                                                           ; 0.000   ; 0.000  ; -10.458  ; -3.861  ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000   ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -11.629 ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.547  ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A     ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; -0.083  ; -1.583 ; N/A      ; N/A     ; 0.000               ;
+------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                      ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 3.024 ; 3.137 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 3.027 ; 3.140 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 3.029 ; 3.142 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.976 ; 3.093 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.966 ; 3.083 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.967 ; 3.084 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 3.010 ; 3.123 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 3.013 ; 3.126 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 3.014 ; 3.127 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 3.025 ; 3.138 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+-------+-------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                         ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_DQ[*]   ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; -0.991 ; -1.543 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; -0.994 ; -1.546 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; -0.996 ; -1.548 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; -0.970 ; -1.528 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; -0.980 ; -1.538 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; -0.971 ; -1.529 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; -0.978 ; -1.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; -0.978 ; -1.530 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; -0.983 ; -1.535 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; -0.984 ; -1.536 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; -0.995 ; -1.547 ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                              ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 2.527  ; 2.240  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 2.449  ; 2.188  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 2.750  ; 2.412  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 2.739  ; 2.401  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 2.735  ; 2.397  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 2.526  ; 2.239  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 2.751  ; 2.413  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 2.516  ; 2.229  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 2.786  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 2.723  ; 2.385  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 2.719  ; 2.381  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 2.434  ; 2.173  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 2.539  ; 2.252  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 2.549  ; 2.262  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 2.716  ; 2.378  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 2.734  ; 2.396  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 2.430  ; 2.169  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 2.733  ; 2.395  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 2.742  ; 2.404  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 2.439  ; 2.178  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 2.724  ; 2.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 2.525  ; 2.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 2.538  ; 2.251  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 5.600  ; 4.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 5.363  ; 4.789  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 7.149  ; 8.043  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 9.814  ; 9.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 9.814  ; 9.187  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 9.554  ; 8.895  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 8.798  ; 8.300  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 8.906  ; 8.196  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 8.409  ; 7.871  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 8.365  ; 7.697  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 10.491 ; 9.578  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 9.917  ; 9.276  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 9.797  ; 9.008  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 9.582  ; 8.966  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 10.491 ; 9.578  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 10.348 ; 9.399  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 10.246 ; 9.386  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 5.948  ; 5.238  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 9.974  ; 9.306  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 8.311  ; 7.583  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 8.385  ; 7.873  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 9.974  ; 9.306  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 9.106  ; 8.505  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 9.589  ; 8.899  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 9.593  ; 8.858  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 6.855  ; 6.175  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -0.558 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -0.945 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                      ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; Data Port     ; Clock Port  ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                       ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+
; SDRAM_A[*]    ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; CLOCK_27[0] ; 0.759  ; 0.603  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; CLOCK_27[0] ; 0.718  ; 0.579  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; CLOCK_27[0] ; 0.886  ; 0.757  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; CLOCK_27[0] ; 0.870  ; 0.741  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; CLOCK_27[0] ; 0.875  ; 0.746  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; CLOCK_27[0] ; 0.758  ; 0.602  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; CLOCK_27[0] ; 0.887  ; 0.758  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; CLOCK_27[0] ; 0.748  ; 0.592  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CKE     ; CLOCK_27[0] ; 0.832  ; 0.743  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; CLOCK_27[0] ; 0.866  ; 0.737  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; CLOCK_27[0] ; 0.863  ; 0.734  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; CLOCK_27[0] ; 0.711  ; 0.572  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; CLOCK_27[0] ; 0.780  ; 0.624  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; CLOCK_27[0] ; 0.770  ; 0.614  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; CLOCK_27[0] ; 0.859  ; 0.730  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; CLOCK_27[0] ; 0.874  ; 0.745  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; CLOCK_27[0] ; 0.703  ; 0.564  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; CLOCK_27[0] ; 0.873  ; 0.744  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; CLOCK_27[0] ; 0.882  ; 0.753  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; CLOCK_27[0] ; 0.712  ; 0.573  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH    ; CLOCK_27[0] ; 0.864  ; 0.735  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML    ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nCAS    ; CLOCK_27[0] ; 0.757  ; 0.601  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nRAS    ; CLOCK_27[0] ; 0.756  ; 0.600  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_nWE     ; CLOCK_27[0] ; 0.769  ; 0.613  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; CLOCK_27[0] ; 2.545  ; 2.329  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; CLOCK_27[0] ; 2.471  ; 2.271  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; LED           ; CLOCK_27[0] ; 3.475  ; 3.530  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; CLOCK_27[0] ; 1.774  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; CLOCK_27[0] ; 2.460  ; 2.432  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; CLOCK_27[0] ; 2.375  ; 2.321  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; CLOCK_27[0] ; 2.026  ; 1.954  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; CLOCK_27[0] ; 1.989  ; 1.903  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[4]     ; CLOCK_27[0] ; 1.855  ; 1.773  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[5]     ; CLOCK_27[0] ; 1.774  ; 1.677  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; CLOCK_27[0] ; 2.361  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; CLOCK_27[0] ; 2.416  ; 2.400  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; CLOCK_27[0] ; 2.369  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; CLOCK_27[0] ; 2.361  ; 2.354  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; CLOCK_27[0] ; 2.625  ; 2.627  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[4]     ; CLOCK_27[0] ; 2.450  ; 2.423  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[5]     ; CLOCK_27[0] ; 2.534  ; 2.519  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS        ; CLOCK_27[0] ; 2.694  ; 2.507  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]      ; CLOCK_27[0] ; 1.893  ; 1.803  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]     ; CLOCK_27[0] ; 1.926  ; 1.850  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]     ; CLOCK_27[0] ; 1.893  ; 1.803  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]     ; CLOCK_27[0] ; 2.163  ; 2.114  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]     ; CLOCK_27[0] ; 2.312  ; 2.257  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[4]     ; CLOCK_27[0] ; 2.234  ; 2.199  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[5]     ; CLOCK_27[0] ; 2.271  ; 2.228  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS        ; CLOCK_27[0] ; 3.101  ; 2.984  ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; CLOCK_27[0] ; -2.008 ;        ; Rise       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; CLOCK_27[0] ;        ; -2.127 ; Fall       ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+---------------+-------------+--------+--------+------------+-----------------------------------------------------------------------+


+-------------------------------------------------------------+
; Progagation Delay                                           ;
+------------+-------------+--------+-------+--------+--------+
; Input Port ; Output Port ; RR     ; RF    ; FR     ; FF     ;
+------------+-------------+--------+-------+--------+--------+
; CONF_DATA0 ; SPI_DO      ; 10.023 ; 9.783 ; 10.558 ; 10.558 ;
+------------+-------------+--------+-------+--------+--------+


+----------------------------------------------------------+
; Minimum Progagation Delay                                ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
+------------+-------------+-------+-------+-------+-------+
; CONF_DATA0 ; SPI_DO      ; 4.639 ; 4.522 ; 5.266 ; 5.266 ;
+------------+-------------+-------+-------+-------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; UART_TX      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------+
; Input Transition Times                                           ;
+---------------+--------------+-----------------+-----------------+
; Pin           ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------+--------------+-----------------+-----------------+
; CLOCK_27[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; UART_RX       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS2       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS3       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SS4       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DO        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_DI        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONF_DATA0    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLOCK_27[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SPI_SCK       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+---------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.33e-06 V                   ; 3.08 V              ; -0.013 V            ; 0.007 V                              ; 0.107 V                              ; 1.54e-09 s                  ; 1.03e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.33e-06 V                  ; 3.08 V             ; -0.013 V           ; 0.007 V                             ; 0.107 V                             ; 1.54e-09 s                 ; 1.03e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.08 V              ; -0.0119 V           ; 0.025 V                              ; 0.13 V                               ; 2.17e-09 s                  ; 1.47e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.08 V             ; -0.0119 V          ; 0.025 V                             ; 0.13 V                              ; 2.17e-09 s                 ; 1.47e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.97e-07 V                   ; 3.09 V              ; -0.0131 V           ; 0.022 V                              ; 0.093 V                              ; 1.48e-09 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.97e-07 V                  ; 3.09 V             ; -0.0131 V          ; 0.022 V                             ; 0.093 V                             ; 1.48e-09 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_HS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; VGA_B[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_B[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; VGA_G[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_G[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; VGA_R[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; AUDIO_R      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCS    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nRAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nCAS   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_nWE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQMH   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQML   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; LED          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; UART_TX      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.28e-07 V                   ; 3.49 V              ; -0.0474 V           ; 0.222 V                              ; 0.267 V                              ; 1.03e-09 s                  ; 6.65e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.28e-07 V                  ; 3.49 V             ; -0.0474 V          ; 0.222 V                             ; 0.267 V                             ; 1.03e-09 s                 ; 6.65e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.49 V              ; -0.0449 V           ; 0.354 V                              ; 0.204 V                              ; 1.36e-09 s                  ; 1.05e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.22e-07 V                  ; 3.49 V             ; -0.0449 V          ; 0.354 V                             ; 0.204 V                             ; 1.36e-09 s                 ; 1.05e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.22e-07 V                   ; 3.5 V               ; -0.0534 V           ; 0.346 V                              ; 0.247 V                              ; 9.06e-10 s                  ; 6.55e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 2.22e-07 V                  ; 3.5 V              ; -0.0534 V          ; 0.346 V                             ; 0.247 V                             ; 9.06e-10 s                 ; 6.55e-10 s                 ; Yes                       ; Yes                       ;
; SPI_DO       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                           ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22764798 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 219      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                            ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27[0]                                                           ; CLOCK_27[0]                                                           ; 85       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2473     ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 120      ; 0        ; 1        ; 0        ;
; CLOCK_27[0]                                                           ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 36       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22764798 ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3        ; 1        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2        ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0        ; 0        ; 1        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] ; 219      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 1        ; 0        ; 0        ; 0        ;
; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; reconfig_pll|altpll_component|auto_generated|pll1|clk[0]              ; 2115     ; 7        ; 42       ; 1        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8033     ; 0        ; 0        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                         ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                            ; To Clock                                                              ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; CLOCK_27[0]                                                           ; 18       ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8033     ; 0        ; 0        ; 0        ;
+-----------------------------------------------------------------------+-----------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 6     ; 6    ;
; Unconstrained Input Ports       ; 18    ; 18   ;
; Unconstrained Input Port Paths  ; 194   ; 194  ;
; Unconstrained Output Ports      ; 61    ; 61   ;
; Unconstrained Output Port Paths ; 116   ; 116  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 11 22:00:52 2019
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {reconfig_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]} {reconfig_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 200 -multiply_by 227 -duty_cycle 50.00 -name {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 50 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 27 -multiply_by 100 -phase -100.00 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2700 -phase -0.01 -duty_cycle 50.00 -name {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]} {pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3]}
Warning (332174): Ignored filter at atari800core.sdc(3): clock|altpll_component|auto_generated|pll1|clk[2] could not be matched with a pin
Warning (332049): Ignored create_generated_clock at atari800core.sdc(3): Argument -source is an empty collection
    Info (332050): create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at atari800core.sdc(5): sdclk_pin could not be matched with a clock
Warning (332049): Ignored set_input_delay at atari800core.sdc(5): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_input_delay at atari800core.sdc(6): Argument -clock is not an object ID
    Info (332050): set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(7): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
Warning (332049): Ignored set_output_delay at atari800core.sdc(8): Argument -clock is not an object ID
    Info (332050): set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
Warning (332174): Ignored filter at atari800core.sdc(9): clock|altpll_component|auto_generated|pll1|clk[0] could not be matched with a clock
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <from> is an empty collection
    Info (332050): set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
Warning (332049): Ignored set_multicycle_path at atari800core.sdc(9): Argument <to> is an empty collection
Warning (332125): Found combinational loop of 2 nodes
    Warning (332126): Node "my_user_io|spi_sck~0|combout"
    Warning (332126): Node "my_user_io|spi_sck~0|datab"
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.851
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.851       -11.629 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.547        -1.547 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.018        -0.018 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.890         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.442         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    33.845         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -1.583
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.583        -1.583 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.355         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.453         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.453         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.455         0.000 CLOCK_27[0] 
    Info (332119):     9.627         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.131
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.131       -10.179 CLOCK_27[0] 
    Info (332119):     2.981         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    10.890         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.429
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.429        -3.861 CLOCK_27[0] 
    Info (332119):     1.589         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.278         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.093
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.093         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.224         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.379         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.274         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.275         0.000 CLOCK_27[0] 
    Info (332119):    40.593         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.506         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.213
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.213       -10.156 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.241        -1.241 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.083        -0.083 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.197         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.785         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    34.170         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -1.383
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.383        -1.383 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.341         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.402         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.403         0.000 CLOCK_27[0] 
    Info (332119):     9.341         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.162
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.162       -10.458 CLOCK_27[0] 
    Info (332119):     3.373         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.418         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.254
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.254        -2.286 CLOCK_27[0] 
    Info (332119):     1.465         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     3.819         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.097
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.097         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.243         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.399         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.279         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    18.270         0.000 CLOCK_27[0] 
    Info (332119):    40.592         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.510         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info: Analyzing Fast 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: SPI_SCK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|read_state.RD_STATE_IDLE was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_ack was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: user_io:my_user_io|sd_dout_strobe was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: sd_card:my_sd_card|write_state.WR_STATE_BUSY was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -2.319
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.319        -5.288 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.181         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.392         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.829         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.668         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    35.614         0.000 CLOCK_27[0] 
Info (332146): Worst-case hold slack is -0.996
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.996        -0.996 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.111         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 CLOCK_27[0] 
    Info (332119):     0.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     8.109         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -0.357
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.357        -3.213 CLOCK_27[0] 
    Info (332119):     6.058         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.588         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case removal slack is -0.378
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.378        -3.402 CLOCK_27[0] 
    Info (332119):     0.686         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.919         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.186
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.186         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.331         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.560         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    16.300         0.000 pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.785         0.000 CLOCK_27[0] 
    Info (332119):    40.634         0.000 reconfig_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119): 44052.600         0.000 pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[3] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 34 warnings
    Info: Peak virtual memory: 562 megabytes
    Info: Processing ended: Wed Sep 11 22:01:01 2019
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:13


